TLB/src/CacheWalker.py

   1 from nmigen import Memory, Module, Signal
   2 from nmigen.cli import main
   3 from math import log
   4
   5 # The purpose of this module is to search a memory block given an
   6 # associativity.
   7 # This module will attempt to find a matching entry when given an address
   8 # and perform permission validation if successful.
   9 #
  10 # Arguments:
  11 #  data_size: (bit count) The size of the data words being processed
  12 #  assoc: (int) The associativity of the memory to be parsed
  13 #  mem: (nmigen.Memory) The memory to be parsed
  14 #
  15 # Return:
  16 #  1. An entry was found -> Return PTE, set hit HIGH, set valid HIGH
  17 #  2. An entry was NOT found -> set hit LOW, set valid HIGH
  18 #  3. A permission fault occurs -> set hit LOW, set valid LOW
  19 class CacheWalker():
  20     def __init__(self, data_size, assoc, mem):
  21         # Parameter parsing
  22         self.assoc = assoc # Assciativity of the cache
  23
  24         self.read_port = mem.read_port
  25         self.write_port = mem.write_port
  26
  27         if (mem_size % assoc != 0):
  28             print("Cache Walker: Memory cannot be distributed between sets")
  29
  30         self.set_count = mem.depth / assoc # Number of sets in memory
  31         self.set_bit_count = log(set_count, 2) # Bit count for sets
  32         # Ensure set_bit_count is fully represented
  33         if(set_count % 2 != 0):
  34             set_bit_count += 1
  35
  36         self.assoc_bits = Signal(set_bit_count) # Bits for associativity
  37
  38         # Inputs
  39         self.vma = Signal(36) # Virtual Memory Address (VMA)
  40
  41         # Output
  42         self.hit = Signal(1) # Denotes if the VMA had a mapped PTE
  43         self.pte = Signal(64) # PTE that was mapped to by the VMA
  44         self.valid = Signal(1) # Denotes if the permissions are correct