super is a keyword: replace with "supermode" in TLB and PermValidator
[soc.git] / TLB / src / PermissionValidator.py
1 from nmigen import Signal
2 from nmigen.cli import main
3
4 class PermissionValidator():
5 """ The purpose of this Module is to check the Permissions of a given PTE
6 against the requested access permissions.
7
8 This module will either validate (by setting the valid bit HIGH)
9 the request or find a permission fault and invalidate (by setting
10 the valid bit LOW) the request
11 """
12
13 def __init__(self, data_size):
14 """ Arguments:
15 * data_size: (bit count) The size of the data words being processed
16
17 Return:
18 * valid HIGH when permissions are correct
19 """
20 # Input
21 self.data = Signal(data_size);
22 self.xwr = Signal(3) # Execute, Write, Read
23 self.supermode = Signal(1) # Supervisor Mode
24 self.super_access = Signal(1) # Supervisor Access
25 self.asid = Signal(15) # Address Space IDentifier (ASID)
26
27 # Output
28 self.valid = Signal(1) # Denotes if the permissions are correct
29
30 def elaborate(self, platform):
31 m = Module()
32 # ASID match or Global Permission
33 with m.If(data[64:78] == self.asid | data[5]):
34 # Check Execute, Write, Read (XWR) Permissions
35 with m.If(data[3] == self.xwr[2] \
36 & data[2] == self.xwr[1] \
37 & data[1] == self.xwr[0]):
38 # Supervisor Logic
39 with m.If(self.supermode):
40 # Valid if entry is not in user mode or supervisor
41 # has Supervisor User Memory (SUM) access via the
42 # SUM bit in the sstatus register
43 m.comb += self.valid.eq(~data[4] | self.super_access)
44 # User logic
45 with m.Else():
46 # Valid if the entry is in user mode only
47 m.comb += self.valid.eq(data[4])
48 with m.Else():
49 m.comb += self.valid.eq(0)
50 with m.Else():
51 m.comb += self.valid.eq(0)