TLB/src/PteEntry.py

   1 from nmigen import Module, Signal
   2 from nmigen.cli import main
   3
   4 class PteEntry():
   5     def __init__(self, asid_size, pte_size):
   6         # Internal
   7         self.asid_start = pte_size
   8         self.asid_end = pte_size + asid_size
   9
  10         # Input
  11         self.i = Signal(asid_size + pte_size)
  12
  13         # Output
  14         self.d = Signal(1) # Dirty bit (From pte)
  15         self.a = Signal(1) # Accessed bit (From pte)
  16         self.g = Signal(1) # Global Access (From pte)
  17         self.u = Signal(1) # User Mode (From pte)
  18         self.xwr = Signal(3) # Execute Read Write (From pte)
  19         self.v = Signal(1) # Valid (From pte)
  20         self.asid = Signal(asid_size) # Associated Address Space IDentifier
  21         self.pte = Signal(pte_size) # Full Page Table Entry
  22
  23     def elaborate(self, platform=None):
  24         m = Module()
  25         # Pull out all control bites from PTE
  26         m.d.comb += [
  27             self.d.eq(self.i[7]),
  28             self.a.eq(self.i[6]),
  29             self.g.eq(self.i[5]),
  30             self.u.eq(self.i[4]),
  31             self.xwr.eq(self.i[1:4]),
  32             self.v.eq(self.i[0])
  33         ]
  34         m.d.comb += self.asid.eq(self.i[self.asid_start:self.asid_end])
  35         m.d.comb += self.pte.eq(self.i[0:self.asid_start])
  36         return m