TLB/src/RegisterFile.py

   1 from nmigen import Array, Module, Signal
   2 from nmigen.lib.coding import Decoder
   3
   4 class RegisterFile():
   5     """ Register File
   6
   7         The purpose of this module is to represent a bank of registers.
   8
   9         Usage:
  10         To Write: Set the address line to the desired register in the file, set
  11         write_enable HIGH, and wait one cycle
  12         To Read: Set the address line to the desired register in the file, set
  13         write_enable LOW, and wait one cycle.
  14     """
  15
  16     def __init__(self, data_size, file_size):
  17         """ Arguments:
  18             * data_size: (bit count) The number of bits in one register
  19             * cam_size: (entry count) the number of registers in this file
  20         """
  21
  22         # Internal
  23         self.register_array = Array(Signal(data_size) for x in range(file_size))
  24
  25         # Input
  26         self.enable = Signal(1)
  27         self.write_enable = Signal(1)
  28         self.address = Signal(max=file_size)
  29         self.data_i = Signal(data_size)
  30
  31         # Output
  32         self.valid = Signal(1)
  33         self.data_o = Signal(data_size)
  34
  35     def elaborate(self, platform=None):
  36         m = Module()
  37
  38         with m.If(self.enable):
  39             # Write Logic
  40             with m.If(self.write_enable):
  41                 m.d.sync += [
  42                     self.valid.eq(0),
  43                     self.data_o.eq(0),
  44                     self.register_array[self.address].eq(self.data_i)
  45                 ]
  46             # Read Logic
  47             with m.Else():
  48                 m.d.sync += [
  49                     self.valid.eq(1),
  50                     self.data_o.eq(self.register_array[self.address])
  51                 ]
  52         # Invalidate results when not enabled
  53         with m.Else():
  54             m.d.sync += [
  55                 self.valid.eq(0),
  56                 self.data_o.eq(0)
  57             ]
  58
  59         return m