TLB/src/TLB.py

   1 from nmigen import Memory, Module, Signal
   2 from nmigen.cli import main
   3
   4 from PermissionValidator import PermissionValidator
   5
   6 # The expected form of the data is
   7 # Item (Bits)
   8 # Tag (N - 79) / ASID (78 - 64) / PTE (63 - 0)
   9
  10 class TLB():
  11     def __init__(self):
  12         # Inputs
  13         self.super = Signal(1) # Supervisor Mode
  14         self.super_access = Signal(1) # Supervisor Access
  15         self.command = Signal(2) # 00=None, 01=Search, 10=Write PTE, 11=Reset
  16         self.xwr = Signal(3) # Execute, Write, Read
  17         self.mode = Signal(4) # 4 bits for access to Sv48 on Rv64
  18         self.asid = Signal(15) # Address Space IDentifier (ASID)
  19         self.vma = Signal(36) # Virtual Memory Address (VMA)
  20         self.pte_in = Signal(64) # To be saved Page Table Entry (PTE)
  21
  22         # Outputs
  23         self.hit = Signal(1) # Denotes if the VMA had a mapped PTE
  24         self.valid = Signal(1) # Denotes if the permissions are correct
  25         self.pteOut = Signal(64) # PTE that was mapped to by the VMA
  26
  27         # Cam simulations
  28         mem_l1 = Memory(113, 32) # L1 TLB cache
  29         read_port_l1 = mem_l1.read_port
  30         write_port_l1 = mem_l1.write_port
  31
  32         mem_l2 = Memory(113, 128) # L2 TLB cache
  33         read_port_l2 = mem_l2.read_port
  34         write_port_l2 = mem_l2.write_port
  35
  36         def elaborate(self, platform):
  37             m = Module()
  38             m.d.submodules.perm_valid = perm_valid = PermissionValidator(113)
  39             m.d.sync += [
  40                 Case(self.command, {
  41                    # Search for PTE
  42                    1: [
  43                        # Check first entry in set
  44                        # TODO make module?
  45                        read_port_l1.addr.eq(vma[0,2]),
  46                        If(read_port_l1.data[0] == 1,
  47                           perm_valid.data.eq(read_port_l1.data),
  48                           perm_valid.xwr.eq(self.xwr),
  49                           perm_valid.super.eq(self.super),
  50                           perm_valid.super_access.eq(self.super_access),
  51                           perm_valid.asid.eq(self.asid),
  52                           self.valid,eq(perm_valid.valid)
  53                        ),
  54                        If(self.valid == 0,
  55                           read_port_l1.addr.eq(vma[0,2] + 1),
  56                           If(read_port_l1.data[0] == 1,
  57                              perm_valid.data.eq(read_port_l1.data),
  58                              perm_valid.xwr.eq(self.xwr),
  59                              perm_valid.super.eq(self.super),
  60                              perm_valid.super_access.eq(self.super_access),
  61                              perm_valid.asid.eq(self.asid),
  62                              self.valid,eq(perm_valid.valid)
  63                           )
  64                        )
  65                        ]
  66                 })
  67             ]
  68             return m
  69
  70 thing = TLB()
  71 print("Gottem")
  72