TLB/test/test_register_file.py

   1 import sys
   2 sys.path.append("../src")
   3 sys.path.append("../../TestUtil")
   4
   5 from nmigen.compat.sim import run_simulation
   6
   7 from RegisterFile import RegisterFile
   8
   9 from test_helper import assert_eq, assert_ne, assert_op
  10
  11 def setRegisterFile(dut, e, we, a, di):
  12     yield dut.enable.eq(e)
  13     yield dut.write_enable.eq(we)
  14     yield dut.address.eq(a)
  15     yield dut.data_i.eq(di)
  16     yield
  17
  18 # Checks the address output of the Cam
  19 # Arguments:
  20 #   dut: The Cam being tested
  21 #   v (Valid): If the output is valid or not
  22 #   op (Operation): (0 => ==), (1 => !=)
  23 def check_valid(dut, v, op):
  24     out_v = yield dut.valid
  25     assert_op("Valid", out_v, v, op)
  26
  27 # Checks the address output of the Cam
  28 # Arguments:
  29 #   dut: The Cam being tested
  30 #   do (Data Out): The current output data
  31 #   op (Operation): (0 => ==), (1 => !=)
  32 def check_data(dut, do, op):
  33     out_do = yield dut.data_o
  34     assert_op("Data Out", out_do, do, op)
  35
  36 # Checks the address output of the Cam
  37 # Arguments:
  38 #   dut: The Cam being tested
  39 #   v (Valid): If the output is valid or not
  40 #   do (Data Out): The current output data
  41 #   v_op (Operation): Operation for the valid assertion (0 => ==), (1 => !=)
  42 #   do_op (Operation): Operation for the data assertion (0 => ==), (1 => !=)
  43 def check_all(dut, v, do, v_op, do_op):
  44     yield from check_valid(dut, v, v_op)
  45     yield from check_data(dut, do, do_op)
  46
  47 def testbench(dut):
  48     # Test write 0
  49     enable = 1
  50     write_enable = 1
  51     address = 0
  52     data = 1
  53     valid = 0
  54     yield from setRegisterFile(dut, enable, write_enable, address, data)
  55     yield
  56     yield from check_all(dut, valid, 0, 0, 0)
  57
  58     # Test read 0
  59     enable = 1
  60     write_enable = 0
  61     address = 0
  62     data = 1
  63     valid = 1
  64     yield from setRegisterFile(dut, enable, write_enable, address, data)
  65     yield
  66     yield from check_all(dut, valid, data, 0, 0)
  67
  68     # Test write 3
  69     enable = 1
  70     write_enable = 1
  71     address = 3
  72     data = 5
  73     valid = 0
  74     yield from setRegisterFile(dut, enable, write_enable, address, data)
  75     yield
  76     yield from check_all(dut, valid, 0, 0, 0)
  77
  78     # Test read 3
  79     enable = 1
  80     write_enable = 0
  81     address = 3
  82     data = 5
  83     valid = 1
  84     yield from setRegisterFile(dut, enable, write_enable, address, data)
  85     yield
  86     yield from check_all(dut, valid, data, 0, 0)
  87
  88     # Test read 0
  89     enable = 1
  90     write_enable = 0
  91     address = 0
  92     data = 1
  93     valid = 1
  94     yield from setRegisterFile(dut, enable, write_enable, address, data)
  95     yield
  96     yield from check_all(dut, valid, data, 0, 0)
  97
  98     # Test overwrite 0
  99     enable = 1
 100     write_enable = 1
 101     address = 0
 102     data = 6
 103     valid = 0
 104     yield from setRegisterFile(dut, enable, write_enable, address, data)
 105     yield
 106     yield from check_all(dut, valid, 0, 0, 0)
 107
 108     # Test read 0
 109     enable = 1
 110     write_enable = 0
 111     address = 0
 112     data = 6
 113     valid = 1
 114     yield from setRegisterFile(dut, enable, write_enable, address, data)
 115     yield
 116     yield from check_all(dut, valid, data, 0, 0)
 117
 118 if __name__ == "__main__":
 119     dut = RegisterFile(4, 4)
 120     run_simulation(dut, testbench(dut), vcd_name="Waveforms/test_register_file.vcd")
 121     print("RegisterFile Unit Test Success")