Fix nmigen dependencies
[soc.git] / flake.nix
1 # The license for this file is included in the `nix` directory next to this file.
2
3 {
4 description = "FOSS CPU/GPU/VPU/SoC all in one, see https://libre-soc.org/";
5
6 inputs.nixpkgs.url = "github:L-as/nixpkgs?ref=alliance"; # for alliance
7 inputs.c4m-jtag.url = "git+https://git.libre-soc.org/git/c4m-jtag.git";
8 inputs.c4m-jtag.flake = false;
9 inputs.nmigen.url = "git+https://git.libre-soc.org/git/nmigen.git";
10 inputs.nmigen.flake = false;
11 inputs.nmigen-soc.url = "git+https://git.libre-soc.org/git/nmigen-soc.git";
12 inputs.nmigen-soc.flake = false;
13
14 outputs = { self, nixpkgs, c4m-jtag, nmigen, nmigen-soc }:
15 let
16 supportedSystems = [ "x86_64-linux" "x86_64-darwin" "aarch64-linux" "aarch64-darwin" ];
17
18 forAllSystems = nixpkgs.lib.genAttrs supportedSystems;
19
20 nixpkgsFor = forAllSystems (system: import nixpkgs { inherit system; overlays = [ self.overlay ]; });
21 in
22 {
23 overlay = final: prev: {
24 python3Packages = prev.python3Packages.override {
25 overrides = pfinal: pprev: {
26 libresoc-ieee754fpu = pfinal.callPackage ./nix/ieee754fpu.nix {};
27 libresoc-openpower-isa = pfinal.callPackage ./nix/openpower-isa.nix {};
28 c4m-jtag = pfinal.callPackage (import ./nix/c4m-jtag.nix { src = c4m-jtag; version = c4m-jtag.lastModifiedDate; }) {};
29 bigfloat = pfinal.callPackage ./nix/bigfloat.nix {};
30 modgrammar = pfinal.callPackage ./nix/modgrammar.nix {};
31 libresoc-nmutil = pfinal.callPackage ./nix/nmutil.nix {};
32
33 nmigen-soc = pprev.nmigen-soc.overrideAttrs (_: {
34 doCheck = false;
35 src = nmigen-soc;
36 setuptoolsCheckPhase = "true";
37 });
38
39 nmigen = pprev.nmigen.overrideAttrs (_: {
40 src = nmigen;
41 });
42 };
43 };
44
45 libresoc-verilog = final.callPackage (import ./nix/verilog.nix { version = self.lastModifiedDate; }) {};
46 };
47
48 packages = forAllSystems (system: {
49 verilog = nixpkgsFor.${system}.libresoc-verilog;
50 openpower-isa = nixpkgsFor.${system}.python3Packages.libresoc-openpower-isa;
51 });
52
53 defaultPackage = forAllSystems (system: self.packages.${system}.verilog);
54 };
55 }