src/experiment/score6600.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Const, Signal, Array, Cat, Elaboratable
   4
   5 from regfile.regfile import RegFileArray, treereduce
   6 from scoreboard.fn_unit import IntFnUnit, FPFnUnit, LDFnUnit, STFnUnit
   7 from scoreboard.fu_fu_matrix import FUFUDepMatrix
   8 from scoreboard.fu_reg_matrix import FURegDepMatrix
   9 from scoreboard.global_pending import GlobalPending
  10 from scoreboard.group_picker import GroupPicker
  11 from scoreboard.issue_unit import IntFPIssueUnit, RegDecode
  12
  13 from compalu import ComputationUnitNoDelay
  14
  15 from alu_hier import ALU
  16 from nmutil.latch import SRLatch
  17
  18 from random import randint
  19
  20 class CompUnits(Elaboratable):
  21
  22     def __init__(self, rwid, n_units):
  23         """ Inputs:
  24
  25             * :rwid:   bit width of register file(s) - both FP and INT
  26             * :n_units: number of ALUs
  27         """
  28         self.n_units = n_units
  29         self.rwid = rwid
  30
  31         self.issue_i = Signal(n_units, reset_less=True)
  32         self.go_rd_i = Signal(n_units, reset_less=True)
  33         self.go_wr_i = Signal(n_units, reset_less=True)
  34         self.busy_o = Signal(n_units, reset_less=True)
  35         self.rd_rel_o = Signal(n_units, reset_less=True)
  36         self.req_rel_o = Signal(n_units, reset_less=True)
  37
  38         self.dest_o = Signal(rwid, reset_less=True)
  39         self.src1_data_i = Signal(rwid, reset_less=True)
  40         self.src2_data_i = Signal(rwid, reset_less=True)
  41
  42     def elaborate(self, platform):
  43         m = Module()
  44
  45         # Int ALUs
  46         add = ALU(self.rwid)
  47         sub = ALU(self.rwid)
  48         m.submodules.comp1 = comp1 = ComputationUnitNoDelay(self.rwid, 1, add)
  49         m.submodules.comp2 = comp2 = ComputationUnitNoDelay(self.rwid, 1, sub)
  50         int_alus = [comp1, comp2]
  51
  52         m.d.comb += comp1.oper_i.eq(Const(0)) # temporary/experiment: op=add
  53         m.d.comb += comp2.oper_i.eq(Const(1)) # temporary/experiment: op=sub
  54
  55         go_rd_l = []
  56         go_wr_l = []
  57         issue_l = []
  58         busy_l = []
  59         req_rel_l = []
  60         rd_rel_l = []
  61         for alu in int_alus:
  62             req_rel_l.append(alu.req_rel_o)
  63             rd_rel_l.append(alu.rd_rel_o)
  64             go_wr_l.append(alu.go_wr_i)
  65             go_rd_l.append(alu.go_rd_i)
  66             issue_l.append(alu.issue_i)
  67             busy_l.append(alu.busy_o)
  68         m.d.comb += self.rd_rel_o.eq(Cat(*rd_rel_l))
  69         m.d.comb += self.req_rel_o.eq(Cat(*req_rel_l))
  70         m.d.comb += self.busy_o.eq(Cat(*busy_l))
  71         m.d.comb += Cat(*go_wr_l).eq(self.go_wr_i)
  72         m.d.comb += Cat(*go_rd_l).eq(self.go_rd_i)
  73         m.d.comb += Cat(*issue_l).eq(self.issue_i)
  74
  75         # connect data register input/output
  76
  77         # merge (OR) all integer FU / ALU outputs to a single value
  78         # bit of a hack: treereduce needs a list with an item named "dest_o"
  79         dest_o = treereduce(int_alus)
  80         m.d.comb += self.dest_o.eq(dest_o)
  81
  82         for i, alu in enumerate(int_alus):
  83             m.d.comb += alu.src1_i.eq(self.src1_data_i)
  84             m.d.comb += alu.src2_i.eq(self.src2_data_i)
  85
  86         return m
  87
  88
  89 class FunctionUnits(Elaboratable):
  90
  91     def __init__(self, n_regs, n_int_alus):
  92         self.n_regs = n_regs
  93         self.n_int_alus = n_int_alus
  94
  95         self.dest_i = Signal(n_regs, reset_less=True) # Dest R# in
  96         self.src1_i = Signal(n_regs, reset_less=True) # oper1 R# in
  97         self.src2_i = Signal(n_regs, reset_less=True) # oper2 R# in
  98
  99         self.dest_rsel_o = Signal(n_regs, reset_less=True) # dest reg (bot)
 100         self.src1_rsel_o = Signal(n_regs, reset_less=True) # src1 reg (bot)
 101         self.src2_rsel_o = Signal(n_regs, reset_less=True) # src2 reg (bot)
 102
 103         self.req_rel_i = Signal(n_int_alus, reset_less = True)
 104         self.g_int_rd_pend_o = Signal(n_regs, reset_less=True)
 105         self.g_int_wr_pend_o = Signal(n_regs, reset_less=True)
 106         self.readable_o = Signal(n_int_alus, reset_less=True)
 107         self.writable_o = Signal(n_int_alus, reset_less=True)
 108
 109         self.go_rd_i = Signal(n_int_alus, reset_less=True)
 110         self.go_wr_i = Signal(n_int_alus, reset_less=True)
 111         self.req_rel_o = Signal(n_int_alus, reset_less=True)
 112         self.fn_issue_i = Signal(n_int_alus, reset_less=True)
 113
 114     def elaborate(self, platform):
 115         m = Module()
 116
 117         n_int_fus = self.n_int_alus
 118
 119         # Integer FU-FU Dep Matrix
 120         intfudeps = FUFUDepMatrix(n_int_fus, n_int_fus)
 121         m.submodules.intfudeps = intfudeps
 122         # Integer FU-Reg Dep Matrix
 123         intregdeps = FURegDepMatrix(n_int_fus, self.n_regs)
 124         m.submodules.intregdeps = intregdeps
 125
 126         m.d.comb += self.g_int_rd_pend_o.eq(intregdeps.rd_pend_o)
 127         m.d.comb += self.g_int_wr_pend_o.eq(intregdeps.wr_pend_o)
 128
 129         m.d.comb += intfudeps.rd_pend_i.eq(self.g_int_rd_pend_o)
 130         m.d.comb += intfudeps.wr_pend_i.eq(self.g_int_wr_pend_o)
 131
 132         m.d.comb += intfudeps.issue_i.eq(self.fn_issue_i)
 133         m.d.comb += intfudeps.go_rd_i.eq(self.go_rd_i)
 134         m.d.comb += intfudeps.go_wr_i.eq(self.go_wr_i)
 135         m.d.comb += self.readable_o.eq(intfudeps.readable_o)
 136         m.d.comb += self.writable_o.eq(intfudeps.writable_o)
 137
 138         # Connect function issue / arrays, and dest/src1/src2
 139         m.d.comb += intregdeps.dest_i.eq(self.dest_i)
 140         m.d.comb += intregdeps.src1_i.eq(self.src1_i)
 141         m.d.comb += intregdeps.src2_i.eq(self.src2_i)
 142
 143         m.d.comb += intregdeps.go_rd_i.eq(self.go_rd_i)
 144         m.d.comb += intregdeps.go_wr_i.eq(self.go_wr_i)
 145         m.d.comb += intregdeps.issue_i.eq(self.fn_issue_i)
 146
 147         m.d.comb += self.dest_rsel_o.eq(intregdeps.dest_rsel_o)
 148         m.d.comb += self.src1_rsel_o.eq(intregdeps.src1_rsel_o)
 149         m.d.comb += self.src2_rsel_o.eq(intregdeps.src2_rsel_o)
 150
 151         return m
 152
 153
 154 class Scoreboard(Elaboratable):
 155     def __init__(self, rwid, n_regs):
 156         """ Inputs:
 157
 158             * :rwid:   bit width of register file(s) - both FP and INT
 159             * :n_regs: depth of register file(s) - number of FP and INT regs
 160         """
 161         self.rwid = rwid
 162         self.n_regs = n_regs
 163
 164         # Register Files
 165         self.intregs = RegFileArray(rwid, n_regs)
 166         self.fpregs = RegFileArray(rwid, n_regs)
 167
 168         # inputs
 169         self.int_store_i = Signal(reset_less=True) # instruction is a store
 170         self.int_dest_i = Signal(max=n_regs, reset_less=True) # Dest R# in
 171         self.int_src1_i = Signal(max=n_regs, reset_less=True) # oper1 R# in
 172         self.int_src2_i = Signal(max=n_regs, reset_less=True) # oper2 R# in
 173         self.reg_enable_i = Signal(reset_less=True) # enable reg decode
 174
 175         self.issue_o = Signal(reset_less=True) # instruction was accepted
 176
 177     def elaborate(self, platform):
 178         m = Module()
 179
 180         m.submodules.intregs = self.intregs
 181         m.submodules.fpregs = self.fpregs
 182
 183         # register ports
 184         int_dest = self.intregs.write_port("dest")
 185         int_src1 = self.intregs.read_port("src1")
 186         int_src2 = self.intregs.read_port("src2")
 187
 188         fp_dest = self.fpregs.write_port("dest")
 189         fp_src1 = self.fpregs.read_port("src1")
 190         fp_src2 = self.fpregs.read_port("src2")
 191
 192         # Int ALUs and Comp Units
 193         n_int_alus = 2
 194         m.submodules.cu = cu = CompUnits(self.rwid, n_int_alus)
 195
 196         # Int FUs
 197         m.submodules.intfus = intfus = FunctionUnits(self.n_regs, n_int_alus)
 198
 199         # Count of number of FUs
 200         n_int_fus = n_int_alus
 201         n_fp_fus = 0 # for now
 202
 203         # Integer Priority Picker 1: Adder + Subtractor
 204         intpick1 = GroupPicker(2) # picks between add and sub
 205         m.submodules.intpick1 = intpick1
 206
 207         # INT/FP Issue Unit
 208         regdecode = RegDecode(self.n_regs)
 209         m.submodules.regdecode = regdecode
 210         issueunit = IntFPIssueUnit(self.n_regs, n_int_fus, n_fp_fus)
 211         m.submodules.issueunit = issueunit
 212
 213         #---------
 214         # ok start wiring things together...
 215         # "now hear de word of de looord... dem bones dem bones dem dryy bones"
 216         # https://www.youtube.com/watch?v=pYb8Wm6-QfA
 217         #---------
 218
 219         #---------
 220         # Issue Unit is where it starts.  set up some in/outs for this module
 221         #---------
 222         m.d.comb += [issueunit.i.store_i.eq(self.int_store_i),
 223                      regdecode.dest_i.eq(self.int_dest_i),
 224                      regdecode.src1_i.eq(self.int_src1_i),
 225                      regdecode.src2_i.eq(self.int_src2_i),
 226                      regdecode.enable_i.eq(self.reg_enable_i),
 227                      issueunit.i.dest_i.eq(regdecode.dest_o),
 228                      self.issue_o.eq(issueunit.issue_o)
 229                     ]
 230         self.int_insn_i = issueunit.i.insn_i # enabled by instruction decode
 231
 232         # connect global rd/wr pending vectors
 233         m.d.comb += issueunit.i.g_wr_pend_i.eq(intfus.g_int_wr_pend_o)
 234         # TODO: issueunit.f (FP)
 235
 236         # and int function issue / busy arrays, and dest/src1/src2
 237         m.d.comb += intfus.dest_i.eq(regdecode.dest_o)
 238         m.d.comb += intfus.src1_i.eq(regdecode.src1_o)
 239         m.d.comb += intfus.src2_i.eq(regdecode.src2_o)
 240
 241         fn_issue_o = issueunit.i.fn_issue_o
 242
 243         m.d.comb += intfus.fn_issue_i.eq(fn_issue_o)
 244         # XXX sync, so as to stop a simulation infinite loop
 245         m.d.comb += issueunit.i.busy_i.eq(cu.busy_o)
 246
 247         #---------
 248         # connect fu-fu matrix
 249         #---------
 250
 251         # Group Picker... done manually for now.  TODO: cat array of pick sigs
 252         go_rd_o = intpick1.go_rd_o
 253         go_wr_o = intpick1.go_wr_o
 254         go_rd_i = intfus.go_rd_i
 255         go_wr_i = intfus.go_wr_i
 256         m.d.comb += go_rd_i[0:2].eq(go_rd_o[0:2]) # add rd
 257         m.d.comb += go_wr_i[0:2].eq(go_wr_o[0:2]) # add wr
 258
 259         # Connect Picker
 260         #---------
 261         #m.d.comb += intpick1.rd_rel_i[0:2].eq(~go_rd_i[0:2] & cu.busy_o[0:2])
 262         m.d.comb += intpick1.rd_rel_i[0:2].eq(cu.rd_rel_o[0:2])
 263         #m.d.comb += intpick1.go_rd_i[0:2].eq(cu.req_rel_o[0:2])
 264         m.d.comb += intpick1.req_rel_i[0:2].eq(cu.req_rel_o[0:2])
 265         int_readable_o = intfus.readable_o
 266         int_writable_o = intfus.writable_o
 267         m.d.comb += intpick1.readable_i[0:2].eq(int_readable_o[0:2])
 268         m.d.comb += intpick1.writable_i[0:2].eq(int_writable_o[0:2])
 269
 270         #---------
 271         # Connect Register File(s)
 272         #---------
 273         print ("intregdeps wen len", len(intfus.dest_rsel_o))
 274         m.d.comb += int_dest.wen.eq(intfus.dest_rsel_o)
 275         m.d.comb += int_src1.ren.eq(intfus.src1_rsel_o)
 276         m.d.comb += int_src2.ren.eq(intfus.src2_rsel_o)
 277
 278         # connect ALUs to regfule
 279         m.d.comb += int_dest.data_i.eq(cu.dest_o)
 280         m.d.comb += cu.src1_data_i.eq(int_src1.data_o)
 281         m.d.comb += cu.src2_data_i.eq(int_src2.data_o)
 282
 283         # connect ALU Computation Units
 284         m.d.comb += cu.go_rd_i[0:2].eq(go_rd_o[0:2])
 285         m.d.comb += cu.go_wr_i[0:2].eq(go_wr_o[0:2])
 286         m.d.comb += cu.issue_i[0:2].eq(fn_issue_o[0:2])
 287
 288         return m
 289
 290
 291     def __iter__(self):
 292         yield from self.intregs
 293         yield from self.fpregs
 294         yield self.int_store_i
 295         yield self.int_dest_i
 296         yield self.int_src1_i
 297         yield self.int_src2_i
 298         yield self.issue_o
 299         #yield from self.int_src1
 300         #yield from self.int_dest
 301         #yield from self.int_src1
 302         #yield from self.int_src2
 303         #yield from self.fp_dest
 304         #yield from self.fp_src1
 305         #yield from self.fp_src2
 306
 307     def ports(self):
 308         return list(self)
 309
 310 IADD = 0
 311 ISUB = 1
 312
 313 class RegSim:
 314     def __init__(self, rwidth, nregs):
 315         self.rwidth = rwidth
 316         self.regs = [0] * nregs
 317
 318     def op(self, op, src1, src2, dest):
 319         src1 = self.regs[src1]
 320         src2 = self.regs[src2]
 321         if op == IADD:
 322             val = (src1 + src2) & ((1<<(self.rwidth))-1)
 323         elif op == ISUB:
 324             val = (src1 - src2) & ((1<<(self.rwidth))-1)
 325         self.regs[dest] = val
 326
 327     def setval(self, dest, val):
 328         self.regs[dest] = val
 329
 330     def dump(self, dut):
 331         for i, val in enumerate(self.regs):
 332             reg = yield dut.intregs.regs[i].reg
 333             okstr = "OK" if reg == val else "!ok"
 334             print("reg %d expected %x received %x %s" % (i, val, reg, okstr))
 335
 336     def check(self, dut):
 337         for i, val in enumerate(self.regs):
 338             reg = yield dut.intregs.regs[i].reg
 339             if reg != val:
 340                 print("reg %d expected %x received %x\n" % (i, val, reg))
 341                 yield from self.dump(dut)
 342                 assert False
 343
 344 def int_instr(dut, alusim, op, src1, src2, dest):
 345     for i in range(len(dut.int_insn_i)):
 346         yield dut.int_insn_i[i].eq(0)
 347     yield dut.int_dest_i.eq(dest)
 348     yield dut.int_src1_i.eq(src1)
 349     yield dut.int_src2_i.eq(src2)
 350     yield dut.int_insn_i[op].eq(1)
 351     yield dut.reg_enable_i.eq(1)
 352     alusim.op(op, src1, src2, dest)
 353
 354
 355 def print_reg(dut, rnums):
 356     rs = []
 357     for rnum in rnums:
 358         reg = yield dut.intregs.regs[rnum].reg
 359         rs.append("%x" % reg)
 360     rnums = map(str, rnums)
 361     print ("reg %s: %s" % (','.join(rnums), ','.join(rs)))
 362
 363
 364 def scoreboard_sim(dut, alusim):
 365     yield dut.int_store_i.eq(0)
 366
 367     for i in range(1, dut.n_regs):
 368         yield dut.intregs.regs[i].reg.eq(4+i*2)
 369         alusim.setval(i, 4+i*2)
 370
 371     instrs = []
 372     if False:
 373         for i in range(2):
 374             src1 = randint(1, dut.n_regs-1)
 375             src2 = randint(1, dut.n_regs-1)
 376             while True:
 377                 dest = randint(1, dut.n_regs-1)
 378                 break
 379                 if dest not in [src1, src2]:
 380                     break
 381             #src1 = 2
 382             #src2 = 3
 383             #dest = 2
 384
 385             op = randint(0, 1)
 386             op = i % 2
 387             op = 0
 388         instrs.append((src1, src2, dest, op))
 389
 390     if False:
 391         instrs.append((2, 3, 3, 0))
 392         instrs.append((5, 3, 3, 1))
 393
 394     if True:
 395         instrs.append((1, 1, 2, 0))
 396         instrs.append((3, 7, 4, 1))
 397         #instrs.append((2, 2, 3, 1))
 398
 399     for i, (src1, src2, dest, op) in enumerate(instrs):
 400
 401         print ("instr %d: %d %d %d %d\n" % (i, op, src1, src2, dest))
 402         yield from int_instr(dut, alusim, op, src1, src2, dest)
 403         yield
 404         while True:
 405             issue_o = yield dut.issue_o
 406             if issue_o:
 407                 for i in range(len(dut.int_insn_i)):
 408                     yield dut.int_insn_i[i].eq(0)
 409                     yield dut.reg_enable_i.eq(0)
 410                 break
 411             print ("busy",)
 412             yield from print_reg(dut, [1,2,3])
 413             yield
 414         yield from print_reg(dut, [1,2,3])
 415
 416     yield
 417     yield from print_reg(dut, [1,2,3])
 418     yield
 419     yield from print_reg(dut, [1,2,3])
 420     yield
 421     yield from print_reg(dut, [1,2,3])
 422     yield
 423     yield from print_reg(dut, [1,2,3])
 424     yield
 425     yield
 426     yield
 427     yield
 428     yield from alusim.check(dut)
 429     yield from alusim.dump(dut)
 430
 431
 432 def explore_groups(dut):
 433     from nmigen.hdl.ir import Fragment
 434     from nmigen.hdl.xfrm import LHSGroupAnalyzer
 435
 436     fragment = dut.elaborate(platform=None)
 437     fr = Fragment.get(fragment, platform=None)
 438
 439     groups = LHSGroupAnalyzer()(fragment._statements)
 440
 441     print (groups)
 442
 443
 444 def test_scoreboard():
 445     dut = Scoreboard(16, 8)
 446     alusim = RegSim(16, 8)
 447     vl = rtlil.convert(dut, ports=dut.ports())
 448     with open("test_scoreboard6600.il", "w") as f:
 449         f.write(vl)
 450
 451     run_simulation(dut, scoreboard_sim(dut, alusim),
 452                         vcd_name='test_scoreboard6600.vcd')
 453
 454
 455 if __name__ == '__main__':
 456     test_scoreboard()