src/scoreboard/addr_match.py

   1 """ Load / Store partial address matcher
   2
   3 Loads and Stores do not need a full match (CAM), they need "good enough"
   4 avoidance.  Around 11 bits on a 64-bit address is "good enough".
   5
   6 The simplest way to use this module is to ignore not only the top bits,
   7 but also the bottom bits as well: in this case (this RV64 processor),
   8 enough to cover a DWORD (64-bit).  that means ignore the bottom 4 bits,
   9 due to the possibility of 64-bit LD/ST being misaligned.
  10
  11 To reiterate: the use of this module is an *optimisation*.  All it has
  12 to do is cover the cases that are *definitely* matches (by checking 11
  13 bits or so), and if a few opportunities for parallel LD/STs are missed
  14 because the top (or bottom) bits weren't checked, so what: all that
  15 happens is: the mis-matched addresses are LD/STd on single-cycles. Big Deal.
  16
  17 However, if we wanted to enhance this algorithm (without using a CAM and
  18 without using expensive comparators) probably the best way to do so would
  19 be to turn the last 16 bits into a byte-level bitmap.  LD/ST on a byte
  20 would have 1 of the 16 bits set.  LD/ST on a DWORD would have 8 of the 16
  21 bits set (offset if the LD/ST was misaligned).  TODO.
  22 """
  23
  24 from nmigen.compat.sim import run_simulation
  25 from nmigen.cli import verilog, rtlil
  26 from nmigen import Module, Signal, Const, Array, Cat, Elaboratable
  27
  28
  29 class PartialAddrMatch(Elaboratable):
  30     """A partial address matcher
  31     """
  32     def __init__(self, n_adr, bitwid):
  33         self.n_adr = n_adr
  34         self.bitwid = bitwid
  35         # inputs
  36         self.addrs_i = Array(Signal(bitwid, name="addr") for i in range(n_adr))
  37         self.addr_we_i = Signal(n_adr) # write-enable for incoming address
  38         self.addr_en_i = Signal(n_adr) # address activated (0 == ignore)
  39
  40         # output
  41         self.addr_match_o = Signal(n_adr)
  42
  43     def elaborate(self, platform):
  44         m = Module()
  45         comb = m.d.comb
  46         sync = m.d.sync
  47
  48         addrs_r = Array(Signal(self.bitwid, "a_r") for i in range(self.n_adr))
  49         addr_en_r = Signal(self.n_adr)
  50
  51         # copy in addresses (and "enable" signals)
  52         for i in range(self.n_adr):
  53             with m.If(self.addr_we_i[i]):
  54                 sync += addrs_r[i].eq(self.addrs_i[i])
  55                 sync += addr_en_r[i].eq(self.addr_en_i[i])
  56
  57         # is there a clash, yes/no
  58         for i in range(self.n_adr):
  59             match = []
  60             for j in range(self.n_adr):
  61                 if i == j:
  62                     match.append(Const(0)) # don't match against self!
  63                 else:
  64                     match.append(addrs_r[i] == addrs_r[j])
  65             comb += self.addr_match_o.eq(Cat(*match).bool() & addr_en_r)
  66
  67         return m
  68
  69     def __iter__(self):
  70         yield from self.addrs_i
  71         yield self.addr_we_i
  72         yield self.addr_en_i
  73         yield self.addr_match_o
  74
  75     def ports(self):
  76         return list(self)
  77
  78
  79 def part_addr_sim(dut):
  80     yield dut.dest_i.eq(1)
  81     yield dut.issue_i.eq(1)
  82     yield
  83     yield dut.issue_i.eq(0)
  84     yield
  85     yield dut.src1_i.eq(1)
  86     yield dut.issue_i.eq(1)
  87     yield
  88     yield dut.issue_i.eq(0)
  89     yield
  90     yield dut.go_rd_i.eq(1)
  91     yield
  92     yield dut.go_rd_i.eq(0)
  93     yield
  94     yield dut.go_wr_i.eq(1)
  95     yield
  96     yield dut.go_wr_i.eq(0)
  97     yield
  98
  99 def test_part_addr():
 100     dut = PartialAddrMatch(3, 10)
 101     vl = rtlil.convert(dut, ports=dut.ports())
 102     with open("test_part_addr.il", "w") as f:
 103         f.write(vl)
 104
 105     run_simulation(dut, part_addr_sim(dut), vcd_name='test_part_addr.vcd')
 106
 107 if __name__ == '__main__':
 108     test_part_addr()