1 """ Load / Store partial address matcher
3 Loads and Stores do not need a full match (CAM), they need "good enough"
4 avoidance. Around 11 bits on a 64-bit address is "good enough".
6 The simplest way to use this module is to ignore not only the top bits,
7 but also the bottom bits as well: in this case (this RV64 processor),
8 enough to cover a DWORD (64-bit). that means ignore the bottom 4 bits,
9 due to the possibility of 64-bit LD/ST being misaligned.
11 To reiterate: the use of this module is an *optimisation*. All it has
12 to do is cover the cases that are *definitely* matches (by checking 11
13 bits or so), and if a few opportunities for parallel LD/STs are missed
14 because the top (or bottom) bits weren't checked, so what: all that
15 happens is: the mis-matched addresses are LD/STd on single-cycles. Big Deal.
17 However, if we wanted to enhance this algorithm (without using a CAM and
18 without using expensive comparators) probably the best way to do so would
19 be to turn the last 16 bits into a byte-level bitmap. LD/ST on a byte
20 would have 1 of the 16 bits set. LD/ST on a DWORD would have 8 of the 16
21 bits set (offset if the LD/ST was misaligned). TODO.
25 > I have used bits <11:6> as they are not translated (4KB pages)
26 > and larger than a cache line (64 bytes).
27 > I have used bits <11:4> when the L1 cache was QuadW sized and
28 > the L2 cache was Line sized.
31 from nmigen
.compat
.sim
import run_simulation
32 from nmigen
.cli
import verilog
, rtlil
33 from nmigen
import Module
, Signal
, Const
, Array
, Cat
, Elaboratable
35 from nmutil
.latch
import latchregister
38 class PartialAddrMatch(Elaboratable
):
39 """A partial address matcher
41 def __init__(self
, n_adr
, bitwid
):
45 self
.addrs_i
= Array(Signal(bitwid
, name
="addr") for i
in range(n_adr
))
46 self
.addr_we_i
= Signal(n_adr
) # write-enable for incoming address
47 self
.addr_en_i
= Signal(n_adr
) # address activated (0 == ignore)
50 self
.addr_match_o
= Array(Signal(n_adr
, name
="match_o") \
51 for i
in range(n_adr
))
53 def elaborate(self
, platform
):
58 addrs_r
= Array(Signal(self
.bitwid
, "a_r") for i
in range(self
.n_adr
))
59 ae_r
= Signal(self
.n_adr
)
61 # copy in addresses (and "enable" signals)
62 for i
in range(self
.n_adr
):
63 latchregister(m
, self
.addrs_i
[i
], addrs_r
[i
], self
.addr_we_i
[i
])
64 latchregister(m
, self
.addr_en_i
[i
], ae_r
[i
], self
.addr_we_i
[i
])
66 # is there a clash, yes/no
67 for i
in range(self
.n_adr
):
69 for j
in range(self
.n_adr
):
71 match
.append(Const(0)) # don't match against self!
73 match
.append(addrs_r
[i
] == addrs_r
[j
])
74 comb
+= self
.addr_match_o
[i
].eq(Cat(*match
) & ae_r
)
79 yield from self
.addrs_i
82 yield from self
.addr_match_o
88 def part_addr_sim(dut
):
89 yield dut
.dest_i
.eq(1)
90 yield dut
.issue_i
.eq(1)
92 yield dut
.issue_i
.eq(0)
94 yield dut
.src1_i
.eq(1)
95 yield dut
.issue_i
.eq(1)
97 yield dut
.issue_i
.eq(0)
99 yield dut
.go_rd_i
.eq(1)
101 yield dut
.go_rd_i
.eq(0)
103 yield dut
.go_wr_i
.eq(1)
105 yield dut
.go_wr_i
.eq(0)
108 def test_part_addr():
109 dut
= PartialAddrMatch(3, 10)
110 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
111 with
open("test_part_addr.il", "w") as f
:
114 run_simulation(dut
, part_addr_sim(dut
), vcd_name
='test_part_addr.vcd')
116 if __name__
== '__main__':