src/soc/bus/test/wb_rw.py

   1 """Wishbone read/write utility routines
   2 """
   3
   4
   5 def wb_write(bus, addr, data, sel=0b1111):
   6
   7     # write wb
   8     yield bus.we.eq(1)
   9     yield bus.cyc.eq(1)
  10     yield bus.stb.eq(1)
  11     #yield bus.sel.eq(0b1111 if sel else 0b1) # 32-bit / 8-bit
  12     yield bus.sel.eq(sel)
  13     yield bus.adr.eq(addr)
  14     yield bus.dat_w.eq(data)
  15
  16     # wait for ack to go high
  17     while True:
  18         ack = yield bus.ack
  19         print ("ack", ack)
  20         if ack:
  21             break
  22         yield # loop until ack
  23         yield bus.stb.eq(0) # drop stb so only 1 thing into pipeline
  24
  25     # leave cyc/stb valid for 1 cycle while writing
  26     yield
  27
  28     # clear out before returning data
  29     yield bus.cyc.eq(0)
  30     yield bus.stb.eq(0)
  31     yield bus.we.eq(0)
  32     yield bus.adr.eq(0)
  33     yield bus.sel.eq(0)
  34     yield bus.dat_w.eq(0)
  35
  36
  37 def wb_read(bus, addr, sel=0b1111):
  38
  39     # read wb
  40     yield bus.cyc.eq(1)
  41     yield bus.stb.eq(1)
  42     yield bus.we.eq(0)
  43     #yield bus.sel.eq(0b1111 if sel else 0b1) # 32-bit / 8-bit
  44     yield bus.sel.eq(sel)
  45     yield bus.adr.eq(addr)
  46
  47     # wait for ack to go high
  48     while True:
  49         ack = yield bus.ack
  50         print ("ack", ack)
  51         if ack:
  52             break
  53         yield # loop until ack
  54         yield bus.stb.eq(0) # drop stb so only 1 thing into pipeline
  55
  56     # get data on same cycle that ack raises
  57     data = yield bus.dat_r
  58
  59     # leave cyc/stb valid for 1 cycle while reading
  60     yield
  61
  62     # clear out before returning data
  63     yield bus.cyc.eq(0)
  64     yield bus.stb.eq(0)
  65     yield bus.we.eq(0)
  66     yield bus.adr.eq(0)
  67     yield bus.sel.eq(0)
  68     return data
  69