set parent pspec to class with XLEN = 64
[soc.git] / src / soc / fu / div / test / test_pipe_ilang.py
1 import unittest
2 from nmigen.cli import rtlil
3 from soc.fu.div.pipe_data import DivPipeSpec, DivPipeKind
4 from soc.fu.div.pipeline import DivBasePipe
5
6
7 class TestPipeIlang(unittest.TestCase):
8 def write_ilang(self, div_pipe_kind):
9 class PPspec:
10 XLEN = 64
11 pps = PPspec()
12 pspec = DivPipeSpec(
13 id_wid=2, div_pipe_kind=div_pipe_kind, parent_pspec=pps)
14 alu = DivBasePipe(pspec)
15 vl = rtlil.convert(alu, ports=alu.ports())
16 with open(f"div_pipeline_{div_pipe_kind.name}.il", "w") as f:
17 f.write(vl)
18
19 def test_div_pipe_core(self):
20 self.write_ilang(DivPipeKind.DivPipeCore)
21
22 def test_fsm_div_core(self):
23 self.write_ilang(DivPipeKind.FSMDivCore)
24
25 def test_sim_only(self):
26 self.write_ilang(DivPipeKind.SimOnly)
27
28
29 if __name__ == "__main__":
30 unittest.main()