src/soc/minerva/wishbone.py

   1 from nmigen import Array, Elaboratable, Module, Record, Signal
   2 from nmigen.hdl.rec import DIR_FANIN, DIR_FANOUT, DIR_NONE
   3 from nmigen.lib.coding import PriorityEncoder
   4 from nmigen.utils import log2_int
   5
   6
   7 __all__ = ["Cycle", "make_wb_layout", "WishboneArbiter"]
   8
   9
  10 class Cycle:
  11     CLASSIC   = 0
  12     CONSTANT  = 1
  13     INCREMENT = 2
  14     END       = 7
  15
  16
  17 def make_wb_layout(spec, cti=True):
  18     addr_wid, mask_wid, data_wid = spec.addr_wid, spec.mask_wid, spec.reg_wid
  19     adr_lsbs = log2_int(mask_wid) # LSBs of addr covered by mask
  20     badwid = spec.addr_wid-adr_lsbs    # MSBs (not covered by mask)
  21     # test if microwatt compatibility is to be enabled
  22     microwatt_compat = (hasattr(spec, "microwatt_compat") and
  23                                (spec.microwatt_compat == True))
  24
  25     res = [
  26     ("adr",   badwid  , DIR_FANOUT),
  27     ("dat_w", data_wid, DIR_FANOUT),
  28     ("dat_r", data_wid, DIR_FANIN),
  29     ("sel",   mask_wid, DIR_FANOUT),
  30     ("cyc",           1, DIR_FANOUT),
  31     ("stb",           1, DIR_FANOUT),
  32     ("ack",           1, DIR_FANIN),
  33     ("we",            1, DIR_FANOUT),
  34     ("err",           1, DIR_FANIN)
  35     ]
  36     # microwatt needs a stall signal (operates in pipeline mode)
  37     if microwatt_compat:
  38         res.append(("stall", 1, DIR_FANIN))
  39     if not cti:
  40         return res
  41     return res + [
  42         ("cti",           3, DIR_FANOUT),
  43         ("bte",           2, DIR_FANOUT),
  44     ]
  45
  46
  47 class WishboneArbiter(Elaboratable):
  48     def __init__(self, pspec):
  49         self.bus = Record(make_wb_layout(pspec))
  50         self._port_map = dict()
  51
  52     def port(self, priority):
  53         if not isinstance(priority, int) or priority < 0:
  54             raise TypeError("Priority must be a non-negative "\
  55                             "integer, not '{!r}'" .format(priority))
  56         if priority in self._port_map:
  57             raise ValueError("Conflicting priority: '{!r}'".format(priority))
  58         port = self._port_map[priority] = Record.like(self.bus)
  59         return port
  60
  61     def elaborate(self, platform):
  62         m = Module()
  63
  64         ports = [port for priority, port in sorted(self._port_map.items())]
  65
  66         for port in ports:
  67             m.d.comb += port.dat_r.eq(self.bus.dat_r)
  68
  69         bus_pe = m.submodules.bus_pe = PriorityEncoder(len(ports))
  70         with m.If(~self.bus.cyc):
  71             for j, port in enumerate(ports):
  72                 m.d.sync += bus_pe.i[j].eq(port.cyc)
  73
  74         source = Array(ports)[bus_pe.o]
  75         m.d.comb += [
  76             self.bus.adr.eq(source.adr),
  77             self.bus.dat_w.eq(source.dat_w),
  78             self.bus.sel.eq(source.sel),
  79             self.bus.cyc.eq(source.cyc),
  80             self.bus.stb.eq(source.stb),
  81             self.bus.we.eq(source.we),
  82             self.bus.cti.eq(source.cti),
  83             self.bus.bte.eq(source.bte),
  84             source.ack.eq(self.bus.ack),
  85             source.err.eq(self.bus.err)
  86         ]
  87
  88         return m