# Input
self.data = Signal(data_size);
self.xwr = Signal(3) # Execute, Write, Read
- self.super = Signal(1) # Supervisor Mode
+ self.supermode = Signal(1) # Supervisor Mode
self.super_access = Signal(1) # Supervisor Access
self.asid = Signal(15) # Address Space IDentifier (ASID)
& data[2] == self.xwr[1] \
& data[1] == self.xwr[0]):
# Supervisor Logic
- with m.If(self.super):
+ with m.If(self.supermode):
# Valid if entry is not in user mode or supervisor
# has Supervisor User Memory (SUM) access via the
# SUM bit in the sstatus register
with m.Else():
m.comb += self.valid.eq(0)
with m.Else():
- m.comb += self.valid.eq(0)
\ No newline at end of file
+ m.comb += self.valid.eq(0)