Show that read_warning is not necessary. But the line should be kept for interfacing?

diff --git a/TLB/src/Cam.py b/TLB/src/Cam.py
index 10d9485e3164f51f80f6a5b5085e293743d41981..7e53dc1207f3648535747d588cca436261cc2488 100644 (file)
--- a/TLB/src/Cam.py
+++ b/TLB/src/Cam.py
@@ -23,6 +23,10 @@ class Cam():
 
         Notes:
         The read and write operations take one clock cycle to complete.
+        Currently the read_warning line is present for interfacing but
+        is not necessary for this design. This module is capable of writing 
+        in the first cycle, reading on the second, and output the correct
+        address on the third. 
     """
 
     def __init__(self, data_size, cam_size):

diff --git a/TLB/test/test_cam.py b/TLB/test/test_cam.py
index cbb06c108ec21c2b74db00e1e750341cd2fcb4b8..4c32707e7f818f7834baae8f94cbb5ddc160042e 100644 (file)
--- a/TLB/test/test_cam.py
+++ b/TLB/test/test_cam.py
@@ -165,7 +165,7 @@ def testbench(dut):
     yield
     yield from check_single_match(dut, single_match, 0)      
     
-    # Read Data 5
+    # Read Hit Data 5
     enable = 1
     write_enable = 0
     address = 1
@@ -174,7 +174,29 @@ def testbench(dut):
     single_match = 0
     yield from set_cam(dut, enable, write_enable, address, data)
     yield
-    yield from check_all(dut, multiple_match, single_match, address,0,0,0)      
+    yield from check_all(dut, multiple_match, single_match, address,0,0,0)  
+    
+    # Verify read_warning is not caused
+    # Write Entry 0
+    enable = 1
+    write_enable = 1
+    address = 0
+    data = 7
+    multiple_match = 0
+    single_match = 0
+    yield from set_cam(dut, enable, write_enable, address, data)   
+    # Note there is no yield we immediately attempt to read in the next cycle
+    
+    # Read Hit Data 7
+    enable = 1
+    write_enable = 0
+    address = 0
+    data = 7
+    multiple_match = 0
+    single_match = 1
+    yield from set_cam(dut, enable, write_enable, address, data) 
+    yield
+    yield from check_single_match(dut, single_match, 0) 
 
     yield