add src1/2 pending outputs

diff --git a/src/scoreboard/fu_reg_matrix.py b/src/scoreboard/fu_reg_matrix.py
index f28e366f932373a8e92a3f3b74ef8629e7b3ddfd..fee803d8804a19b7f0c5ff4cd597d92a52fc9ae2 100644 (file)
--- a/src/scoreboard/fu_reg_matrix.py
+++ b/src/scoreboard/fu_reg_matrix.py
@@ -47,6 +47,8 @@ class FURegDepMatrix(Elaboratable):
         # for Function Unit "forward progress" (vertical), per-FU
         self.wr_pend_o = Signal(n_fu_row, reset_less=True) # wr pending (right)
         self.rd_pend_o = Signal(n_fu_row, reset_less=True) # rd pending (right)
+        self.rd_src1_pend_o = Signal(n_fu_row, reset_less=True) # src1 pending
+        self.rd_src2_pend_o = Signal(n_fu_row, reset_less=True) # src2 pending
 
     def elaborate(self, platform):
         m = Module()
@@ -79,6 +81,8 @@ class FURegDepMatrix(Elaboratable):
         # ---
         wr_pend = []
         rd_pend = []
+        rd_src1_pend = []
+        rd_src2_pend = []
         for fu in range(self.n_fu_row):
             fup = fupend[fu]
             dest_fwd_o = []
@@ -98,10 +102,14 @@ class FURegDepMatrix(Elaboratable):
             # accumulate FU Vector outputs
             wr_pend.append(fup.reg_wr_pend_o)
             rd_pend.append(fup.reg_rd_pend_o)
+            src1_pend.append(fup.reg_rd_src1_pend_o)
+            src2_pend.append(fup.reg_rd_src2_pend_o)
 
         # ... and output them from this module (vertical, width=FUs)
         m.d.comb += self.wr_pend_o.eq(Cat(*wr_pend))
         m.d.comb += self.rd_pend_o.eq(Cat(*rd_pend))
+        m.d.comb += self.rd_src1_pend_o.eq(Cat(*rd_src1_pend))
+        m.d.comb += self.rd_src2_pend_o.eq(Cat(*rd_src2_pend))
 
         # ---
         # connect Reg Selection vector

diff --git a/src/scoreboard/fu_wr_pending.py b/src/scoreboard/fu_wr_pending.py
index 9b177ff041db5b470f8c2fba9ad0f9242fd7bb90..abfca25f7257b33ea87f21174d2e4ffd7db5c638 100644 (file)
--- a/src/scoreboard/fu_wr_pending.py
+++ b/src/scoreboard/fu_wr_pending.py
@@ -13,11 +13,15 @@ class FU_RW_Pend(Elaboratable):
 
         self.reg_wr_pend_o = Signal(reset_less=True)
         self.reg_rd_pend_o = Signal(reset_less=True)
+        self.reg_rd_src1_pend_o = Signal(reset_less=True)
+        self.reg_rd_src2_pend_o = Signal(reset_less=True)
 
     def elaborate(self, platform):
         m = Module()
-        srces = Cat(self.src1_fwd_i, self.src2_fwd_i)
         m.d.comb += self.reg_wr_pend_o.eq(self.dest_fwd_i.bool())
-        m.d.comb += self.reg_rd_pend_o.eq(srces.bool())
+        m.d.comb += self.reg_rd_src1_pend_o.eq(self.src1_fwd_i.bool())
+        m.d.comb += self.reg_rd_src2_pend_o.eq(self.src2_fwd_i.bool())
+        m.d.comb += self.reg_rd_pend_o.eq(self.reg_rd_src1_pend_o |
+                                          self.reg_rd_src2_pend_o)
         return m