disable writethru for now

diff --git a/src/regfile/regfile.py b/src/regfile/regfile.py
index 7d8ead9e2d3e3b673b6e41a7074ffaab29f324f3..29fbda65b14ad4546e264f3a57f31af06389c900 100644 (file)
--- a/src/regfile/regfile.py
+++ b/src/regfile/regfile.py
@@ -10,8 +10,9 @@ import operator
 
 
 class Register(Elaboratable):
-    def __init__(self, width):
+    def __init__(self, width, writethru=False):
         self.width = width
+        self.writethru = writethru
         self._rdports = []
         self._wrports = []
 
@@ -35,14 +36,17 @@ class Register(Elaboratable):
 
         # read ports. has write-through detection (returns data written)
         for rp in self._rdports:
-            wr_detect = Signal(reset_less=False)
             with m.If(rp.ren):
-                m.d.comb += wr_detect.eq(0)
-                for wp in self._wrports:
-                    with m.If(wp.wen):
-                        m.d.comb += rp.data_o.eq(wp.data_i)
-                        m.d.comb += wr_detect.eq(1)
-                with m.If(~wr_detect):
+                if self.writethru:
+                    wr_detect = Signal(reset_less=False)
+                    m.d.comb += wr_detect.eq(0)
+                    for wp in self._wrports:
+                        with m.If(wp.wen):
+                            m.d.comb += rp.data_o.eq(wp.data_i)
+                            m.d.comb += wr_detect.eq(1)
+                    with m.If(~wr_detect):
+                        m.d.comb += rp.data_o.eq(reg)
+                else:
                     m.d.comb += rp.data_o.eq(reg)
 
         # write ports, don't allow write to address 0 (ignore it)