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Handle newer nMigen adding a "bench" hierarchy root in VCD files
author
Cesar Strauss
<cestrauss@gmail.com>
Sun, 1 Jan 2023 12:30:41 +0000
(09:30 -0300)
committer
Cesar Strauss
<cestrauss@gmail.com>
Sun, 1 Jan 2023 12:30:41 +0000
(09:30 -0300)
src/soc/experiment/test/test_compalu_multi.py
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diff --git
a/src/soc/experiment/test/test_compalu_multi.py
b/src/soc/experiment/test/test_compalu_multi.py
index 39b24147fb5bdef50ba77e822719dcb1ab11c762..2f2c51d1c18888187c4d540e54fb5604d9b8e236 100644
(file)
--- a/
src/soc/experiment/test/test_compalu_multi.py
+++ b/
src/soc/experiment/test/test_compalu_multi.py
@@
-534,14
+534,14
@@
def test_compunit_fsm():
'n_data_o[7:0]',
({'submodule': 'n'},
['n_o_valid', 'n_i_ready'])])]),
'n_data_o[7:0]',
({'submodule': 'n'},
['n_o_valid', 'n_i_ready'])])]),
- ('debug', {'module': '
top
'},
+ ('debug', {'module': '
bench
'},
['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])]
write_gtkw(
"test_compunit_fsm1.gtkw",
"test_compunit_fsm1.vcd",
traces, style,
['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])]
write_gtkw(
"test_compunit_fsm1.gtkw",
"test_compunit_fsm1.vcd",
traces, style,
- module='top.cu'
+ module='
bench.
top.cu'
)
m = Module()
alu = Shifter(8)
)
m = Module()
alu = Shifter(8)
@@
-667,7
+667,7
@@
def test_compunit_regspec3():
"test_compunit_regspec3.vcd",
traces, style,
clk_period=1e-6,
"test_compunit_regspec3.vcd",
traces, style,
clk_period=1e-6,
- module='top.cu')
+ module='
bench.
top.cu')
inspec = [('INT', 'a', '0:15'),
('INT', 'b', '0:15'),
inspec = [('INT', 'a', '0:15'),
('INT', 'b', '0:15'),
@@
-738,14
+738,14
@@
def test_compunit_regspec1():
('next port', 'out', [
'alu_o[15:0]', 'o_valid', 'i_ready',
'alu_o_ok', 'alu_cr_ok'])]),
('next port', 'out', [
'alu_o[15:0]', 'o_valid', 'i_ready',
'alu_o_ok', 'alu_cr_ok'])]),
- ('debug', {'module': '
top
'},
+ ('debug', {'module': '
bench
'},
['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])]
write_gtkw("test_compunit_regspec1.gtkw",
"test_compunit_regspec1.vcd",
traces, style,
clk_period=1e-6,
['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])]
write_gtkw("test_compunit_regspec1.gtkw",
"test_compunit_regspec1.vcd",
traces, style,
clk_period=1e-6,
- module='top.cu')
+ module='
bench.
top.cu')
inspec = [('INT', 'a', '0:15'),
('INT', 'b', '0:15')]
inspec = [('INT', 'a', '0:15'),
('INT', 'b', '0:15')]