* add in a new PRE_IDLE state into issue FSM (to allow pc_at_reset to
get a word in edgeways)
* set nia to pc_at_reset on core_rst (not 0x0)
* add in a terrible hack where the STATE regfile entry for PC is
shifted down by one.
absolutely no frickin idea why that is needed
microwatt_external_core_bram:
python3 src/soc/simple/issuer_verilog.py --microwatt-compat \
--enable-mmu \
microwatt_external_core_bram:
python3 src/soc/simple/issuer_verilog.py --microwatt-compat \
--enable-mmu \
- --pc-reset 0xFFF00000 \
+ --pc-reset 0xFF000000 \
external_core_top.v
# build the litex libresoc SoC without 4k SRAMs
external_core_top.v
# build the litex libresoc SoC without 4k SRAMs
self.msr_at_reset = pspec.msr_reset
if hasattr(pspec, "pc_reset") and isinstance(pspec.pc_reset, int):
self.pc_at_reset = pspec.pc_reset
self.msr_at_reset = pspec.msr_reset
if hasattr(pspec, "pc_reset") and isinstance(pspec.pc_reset, int):
self.pc_at_reset = pspec.pc_reset
- state_resets = [self.pc_at_reset, # PC at reset
+ state_resets = [self.pc_at_reset>>1, # PC at reset
self.msr_at_reset, # MSR at reset
0x0, # SVSTATE at reset
0x0, # DEC at reset
self.msr_at_reset, # MSR at reset
0x0, # SVSTATE at reset
0x0, # DEC at reset
with m.If(core_rst):
m.d.sync += self.cur_state.eq(0)
# and, sigh, set configured values, which are also done in regfile
with m.If(core_rst):
m.d.sync += self.cur_state.eq(0)
# and, sigh, set configured values, which are also done in regfile
+ # XXX ??? what the hell is the shift for??
m.d.sync += self.cur_state.pc.eq(self.core.pc_at_reset)
m.d.sync += self.cur_state.msr.eq(self.core.msr_at_reset)
m.d.sync += self.cur_state.pc.eq(self.core.pc_at_reset)
m.d.sync += self.cur_state.msr.eq(self.core.msr_at_reset)
easy understanding) come later.
"""
easy understanding) come later.
"""
- def fetch_fsm(self, m, dbg, core, nia, is_svp64_mode,
+ def fetch_fsm(self, m, dbg, core, core_rst, nia, is_svp64_mode,
fetch_pc_o_ready, fetch_pc_i_valid,
fetch_insn_o_valid, fetch_insn_i_ready):
"""fetch FSM
fetch_pc_o_ready, fetch_pc_i_valid,
fetch_insn_o_valid, fetch_insn_i_ready):
"""fetch FSM
# allow fetch to not run at startup due to I-Cache reset not
# having time to settle. power-on-reset holds dbg.core_stopped_i
with m.State("PRE_IDLE"):
# allow fetch to not run at startup due to I-Cache reset not
# having time to settle. power-on-reset holds dbg.core_stopped_i
with m.State("PRE_IDLE"):
- with m.If(~dbg.core_stopped_i & ~dbg.core_stop_o):
+ with m.If(~dbg.core_stopped_i & ~dbg.core_stop_o & ~core_rst):
m.next = "IDLE"
# waiting (zzz)
m.next = "IDLE"
# waiting (zzz)
with m.FSM(name="issue_fsm"):
with m.FSM(name="issue_fsm"):
+ with m.State("PRE_IDLE"):
+ with m.If(~dbg.core_stop_o & ~core_rst):
+ m.next = "ISSUE_START"
+
# sync with the "fetch" phase which is reading the instruction
# at this point, there is no instruction running, that
# could inadvertently update the PC.
# sync with the "fetch" phase which is reading the instruction
# at this point, there is no instruction running, that
# could inadvertently update the PC.
# Issue is where the VL for-loop # lives. the ready/valid
# signalling is used to communicate between the four.
# Issue is where the VL for-loop # lives. the ready/valid
# signalling is used to communicate between the four.
- self.fetch_fsm(m, dbg, core, nia, is_svp64_mode,
+ self.fetch_fsm(m, dbg, core, core_rst, nia, is_svp64_mode,
fetch_pc_o_ready, fetch_pc_i_valid,
fetch_insn_o_valid, fetch_insn_i_ready)
fetch_pc_o_ready, fetch_pc_i_valid,
fetch_insn_o_valid, fetch_insn_i_ready)
exec_insn_i_valid, exec_insn_o_ready,
exec_pc_o_valid, exec_pc_i_ready)
exec_insn_i_valid, exec_insn_o_ready,
exec_pc_o_valid, exec_pc_i_ready)
- # whatever was done above, over-ride it if core reset is held
+ # whatever was done above, over-ride it if core reset is held.
+ # set NIA to pc_at_reset
+ sync += nia.eq(self.core.pc_at_reset)