make fn unit invert readable, however qualify with rd latch

diff --git a/src/experiment/cscore.py b/src/experiment/cscore.py
index 61f7ec099878976c4261f845b36204a5e5497409..707a0ea35bb7c59059533e790ab9150b9ea2b59c 100644 (file)
--- a/src/experiment/cscore.py
+++ b/src/experiment/cscore.py
@@ -326,7 +326,7 @@ def scoreboard_sim(dut, alusim):
         #dest = 2 
 
         op = randint(0, 1)
-        op = i
+        op = 0
         print ("random %d: %d %d %d %d\n" % (i, op, src1, src2, dest))
         yield from int_instr(dut, alusim, op, src1, src2, dest)
         yield from print_reg(dut, [3,4,5])

diff --git a/src/scoreboard/fn_unit.py b/src/scoreboard/fn_unit.py
index d706b7f1ce3d4ce038c5fdbb486e61123fff8510..3edabbde16eb2c2dc41eb4b5f9e8a4d508835090 100644 (file)
--- a/src/scoreboard/fn_unit.py
+++ b/src/scoreboard/fn_unit.py
@@ -163,9 +163,9 @@ class FnUnit(Elaboratable):
         # readable output signal
         g_rd = Signal(self.reg_width, reset_less=True)
         ro = Signal(reset_less=True)
-        m.d.comb += g_rd.eq(~self.g_wr_pend_i & self.rd_pend_o)
-        m.d.comb += ro.eq(g_rd.bool())
-        m.d.comb += self.readable_o.eq(ro)
+        m.d.comb += g_rd.eq(self.g_wr_pend_i & self.rd_pend_o)
+        m.d.comb += ro.eq(~g_rd.bool())
+        m.d.comb += self.readable_o.eq(ro & rd_l.q)
 
         # writable output signal
         g_wr_v = Signal(self.reg_width, reset_less=True)