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comment about por_clk
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 5 Jun 2021 12:20:00 +0000 (12:20 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 5 Jun 2021 12:20:00 +0000 (12:20 +0000)
experiments9/tsmc_c018/doDesign.py patch | blob | history

diff --git a/experiments9/tsmc_c018/doDesign.py b/experiments9/tsmc_c018/doDesign.py
index 816b1de622631c79c3ad022edd64c3f6f6ad8348..6e9070093d72b60a026bf5cb737020188412f81b 100644 (file)
--- a/experiments9/tsmc_c018/doDesign.py
+++ b/experiments9/tsmc_c018/doDesign.py
@@ -228,6 +228,7 @@ def scriptMain (**kw):
         ls180Conf.coreSize = (coreSizeX, coreSizeY)
         ls180Conf.chipSize = (coreSizeX + chipBorder + u(5.0), coreSizeY + chipBorder - u(0.04) )
        #ls180Conf.useHTree( 'core.subckt_12941_test_issuer.ti_coresync_clk' )
+        # XXX this is probably just por_clk not core.por_clk
         ls180Conf.useHTree( 'core.por_clk' )
         ls180Conf.useHTree( 'jtag_tck_from_pad' )