180nm_Oct2020/interfaces.mdwn

   1 # Interfaces for the 180nm Oct2020 ASIC
   2
   3 [[ls180]] actual interfaces
   4
   5 [List Link](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006355.html)
   6
   7 Bugreport and discussion at <https://bugs.libre-soc.org/show_bug.cgi?id=304>
   8
   9 These are bare minimum viability:
  10 These should be easily doable with LiteX.
  11
  12 * [[shakti/m_class/UART]]
  13 * [[shakti/m_class/I2C]]
  14 * [[shakti/m_class/GPIO]]
  15 * [[shakti/m_class/SPI]]
  16 * [[shakti/m_class/QSPI]]
  17 * [[shakti/m_class/LPC]]
  18 * [[shakti/m_class/EINT]]
  19 * [[shakti/m_class/JTAG]]
  20
  21 Under consideration:
  22
  23 * [[shakti/m_class/sdram]] see <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006374.html>
  24
  25 # Secondary priorities
  26
  27 * a pinmux
  28 * USB - again doable with LiteX. I'm talking to Enjoy Digital about what
  29   USB PHYs LiteX supports. - Yehowshua
  30 * SERDES for Ethernet - using LiteX and
  31   [Marvell PHY](https://www.mouser.com/ProductDetail/Marvell/88E1512-A0-NNP2I000?qs=vdi0iO8H4N0XzuXqBRxTqg%3D%3D)
  32 * Noting that a SERDES to RGMII PHY is $20 (kinda expensive for total cost
  33   of an SBC), we can instead do Eth over USB like the original RPI. This
  34   moves the complexity to software - could make doing eth things during
  35   boot loader a little more complex.
  36
  37 Jacob notes:
  38
  39 I haven't checked but I'm 99% sure that we will need to implement standard
  40 Power atomics, fences, ll/sc (including 128-bit version), cache flushes,
  41 and non-cacheable load/store operations if we want to support Linux on our
  42 october test chip.
  43
  44 <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006407.html>
  45
  46 ## Alternate USB Interface Options
  47  - https://github.com/im-tomu/valentyusb
  48  - https://github.com/lambdaconcept/lambdaUSB
  49  - https://github.com/greatscottgadgets/luna