180nm_Oct2020.mdwn

   1 # 180 nm ASIC plan for Oct 2020
   2
   3 This page is for discussion of what we can aim for and reasonably achieve.
   4 To be expanded with links to bugreports
   5
   6 ## Minimum viability
   7
   8 * a Wishbone interface.  this allows us to drop *directly* into
   9   already-written Litex "SOC" infrastructure (leaving all of us free to
  10   focus on the essentials)
  11 * the dependency matrices are essential.
  12 * a Branch Function Unit is essential (minimum of 1)
  13 * Load/Store Function Units are essential
  14 * so are multiple register file files (SPRs, Condition Regs, 32x INT Regs)
  15 * the integer pipelines (integer and logic instructions) are essential
  16   (the FP ones not so much)
  17 * a very very basic Branch Prediction system (fixed, but observing POWER
  18   branch "hints")
  19 * a very very basic Common Data Bus infrastructure.
  20 * a TLB and MMU are not strictly essential (not for a proof-of-concept ASIC)
  21 * neither in some ways is a L1 cache
  22 * [[180nm_oct2020/interfaces]] we need as a bare minimum include GPIO, EINT, SPI and QSPI,
  23   I2C, UART16550, LPC (from Raptor Engineering) and that actually might
  24   even be it.
  25
  26 ## Secondary priorities
  27
  28 * a PLL (this is quite a lot however it turns the ASIC from a 24mhz
  29   design into a 300mhz design)
  30 * a TLB and MMU (in combination with a PLL if it is GNU/Linux OS capable
  31   we have an actual viable *saleable product*, immediately)
  32 * dual L1 Caches with the 2x 128-bit-wide L0CacheBuffer to merge 8x LD/STs
  33 * multiple Common Data Buses to / from the RegFile along with a 4x
  34   "Striped" HI/LO-32-ODD/EVEN access pattern.
  35 * multi-issue
  36 * PartitionedSignal-based integer pipelines
  37 * an FP regfile and associated FP pipelines
  38 * SV compliance
  39 * 128x INT/FP registers
  40 * GPU-style opcodes - Jacob mentioned Texturisation opcodes as being
  41   more important than e.g. SIN/COS.
  42 * additional interfaces such as RGB/TTL, SDRAM, HyperRAM, RGMII, SD/MMC,
  43   USB-ULPI
  44 * a pinmux
  45
  46 # Available people
  47
  48 * Rudi from <http://asics.ws> to cover the interface set
  49 * [[lkcl]] for the scoreboard systems
  50 * [[programmerjake]] TODO
  51 * [[Yehowshua_Immanuel]] TODO
  52 * [[mtnolan]] TODO
  53 * [[tplaten]] TODO
  54 * [[jock_tanner]] TODO
  55 * MarketNext TODO
  56