180nm_Oct2020.mdwn

   1 # 180 nm ASIC plan for Oct 2020
   2
   3 This page is for discussion of what we can aim for and reasonably achieve.
   4 To be expanded with links to bugreports
   5
   6 ## Minimum viability
   7
   8 * a Wishbone interface.  this allows us to drop *directly* into
   9   already-written Litex "SOC" infrastructure (leaving all of us free to
  10   focus on the essentials)
  11 * the dependency matrices are essential.
  12 * a Branch Function Unit is essential (minimum of 1)
  13 * Load/Store Function Units are essential
  14 * so are multiple register file files (SPRs, Condition Regs, 32x INT Regs)
  15 * the integer pipelines (integer and logic instructions) are essential
  16   (the FP ones not so much)
  17   <https://bugs.libre-soc.org/show_bug.cgi?id=305>
  18 * a very very basic Branch Prediction system (fixed, but observing POWER
  19   branch "hints")
  20 * a very very basic Common Data Bus infrastructure.
  21 * a TLB and MMU are not strictly essential (not for a proof-of-concept ASIC)
  22 * neither in some ways is a L1 cache
  23 * [[180nm_Oct2020/interfaces]] we need as a bare minimum include JTAG,
  24   GPIO, EINT, SPI and QSPI, I2C, UART16550, LPC (from Raptor Engineering)
  25   and that actually might even be it.
  26
  27 ## Secondary priorities
  28
  29 * a PLL (this is quite a lot however it turns the ASIC from a 24mhz
  30   design into a 300mhz design)
  31 * a TLB and MMU (in combination with a PLL if it is GNU/Linux OS capable
  32   we have an actual viable *saleable product*, immediately)
  33 * dual L1 Caches with the 2x 128-bit-wide L0CacheBuffer to merge 8x LD/STs
  34 * multiple Common Data Buses to / from the RegFile along with a 4x
  35   "Striped" HI/LO-32-ODD/EVEN access pattern.
  36 * multi-issue
  37 * PartitionedSignal-based integer pipelines
  38 * an FP regfile and associated FP pipelines
  39 * SV compliance
  40 * 128x INT/FP registers
  41 * GPU-style opcodes - Jacob mentioned Texturisation opcodes as being
  42   more important than e.g. SIN/COS.
  43 * additional interfaces such as RGB/TTL, SDRAM, HyperRAM, RGMII, SD/MMC,
  44   USB-ULPI
  45 * a pinmux
  46
  47 # Available people
  48
  49 * Rudi from <http://asics.ws> to cover the interface set
  50 * [[lkcl]] for the scoreboard systems
  51 * [[programmerjake]] TODO
  52 * [[Yehowshua_Immanuel]] - Delegate interfaces a
  53 * [[mnolan]] pipelines
  54 * [[tplaten]] TODO
  55 * [[jock_tanner]] TODO
  56 * MarketNext TODO
  57