22nm_PowerPI.mdwn

   1 # Specs for 22/28nm SOC
   2
   3 **Overall goal: an SoC that is capable of meeting multiple markets:**
   4
   5 * Basic "Pi" style SBC role (aka POWER-Pi)
   6 * Libre-style smartphone, tablet, netbook and chromebook products
   7   - Pine64, Purism, FairPhone, many others
   8 * Baseboard Management Controller (BMC) replacement for ASpeed products
   9   - including PCIe Video Card capability after BMC Boot
  10 * Mid-end low-cost Graphics Card with reasonable 3D and VPU capabilities
  11   - This as a sub-goal of the BMC functionality (stand-alone)
  12
  13 By meeting the needs of multiple markets in a single SoC the product has
  14 broader appeal yet amortises the NREs across all of them.  This is
  15 industry-standard practice: ST Micro and ATMEL use the exact same die in
  16 up to 12-14 different products.
  17
  18 **Timeframe from when funding is received:**
  19
  20 * 6-8 months for PHY negotiation and supply by IP Vendors (DDR4 is always
  21   custom-tailored by the supplier)
  22 * 6-8 months development (in parallel with PHY negotiation)
  23 * 3-4 months FPGA proof-of-concept (partial overlap with above)
  24 * 4-6 months layout development once design is frozen (partial overlap with
  25   above)
  26
  27 Total: 12-18 months development time.  **This is industry-standard**
  28
  29 **NREs:**
  30
  31 These are ballpark estimates:
  32
  33 * USD 250,000 for layout software licensing (Cadence / Synopsis / Mentor)
  34 * USD 400,000 for engineer to perform layout to GDS-II
  35 * USD 1,000,000 for (LP)DDR3/4 which includes customisation by IP vendor
  36 * USD 250,000 for Libre-licensed DDR firmware (normally closed binary)
  37 * USD 250,000 for USB3/C
  38 * USD 250,000 for HDMI PHY (includes HDCP closed firmware: DVI may be better)
  39 * USD 50,000 for PCIe PHY
  40 * USD 50,000 for RGMII Ethernet PHY
  41 * USD 50,000 for Libre-licensed PCIe firmware (normally closed binary)
  42 * USD 2,000,000 for Engineers
  43 * USD 2,000,000 for 22nm Production Masks (1,000,000 for 28nm)
  44 * USD 200,000 per 22nm MPW Shuttle Service (test ASICs.  28nm is 100,000)
  45 * USD 200,000 estimated for other PHYs (UART, SD/MMC, I2C, SPI)
  46
  47 Total is around USD 7 million.
  48
  49 Note that this is a bare minimum and may require re-spins of the production
  50 masks.  A safety margin is recommended to cover at least 2 additional
  51 re-spins.  Business Operating costs bring the total realistically
  52 to around USD 12 million.
  53
  54 Production cost is expected to be around the $3.50 to $4 mark meaning
  55 that a sale price of around $12-$13 will require **1 million units**
  56 sold to recover the NREs.
  57
  58 **Even if the SoC used an off-the-shelf OpenPOWER core these development
  59 NREs are still required**
  60
  61 # Functionality
  62
  63  - 4 Core dual-issue LibreSOC OpenPOWER CPU
  64  - SimpleV Capability with VPU and GPU Instructions *no need for separate GPU*
  65  - IOMMU
  66  - PCIe Host Controller
  67  - PCIe Slave controller (RaptorCS wants to use LibreSOC as a Graphics Card
  68     on their TALOS-II motherboards)
  69  - BMC capability (OpenBMC / LibreBMC) - enables LibreSOC to replace the
  70    closed source ASpeed BMC product range, booting up
  71  - RGB/TTL framebuffer VGA/LCD PHY from Richard Herveille, RoaLogic.
  72  - Pinmux for mapping multiple I/O functions to pins (standard fare
  73    for SoCs, to reduce pincount)
  74
  75 # Interfaces
  76
  77 ## Advanced
  78
  79  - SERDES - 10rx, 14tx
  80    - 4tx, 4rx for [OMI(DDR4](https://openpowerfoundation.org/wp-content/uploads/2018/10/Jeff-Steuchli.OpenCAPI-OPS-OMI.pdf) on top of SERDES with OpenCAPI protocol) @5GHz
  81    - 4tx, 4rx for PCIe and other CAPI devices
  82    - 3tx for HDMI (note: requires HDMI Trademark Licensing and Compliance Testing.  DVI is an alternative)
  83  - [OpenFSI](https://openpowerfoundation.org/?resource_lib=field-replaceable-unit-fru-service-interface-fsi-openfsi-specification) instead of JTAG
  84    - [Raptor HDL](https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga)
  85    - [Raptor Libsigrok](https://gitlab.raptorengineering.com/raptor-engineering-public/dsview/-/tree/master/libsigrokdecode4DSL/decoders/fsi)
  86  - USB-OTG / USB2 - [Luna USB](https://github.com/greatscottgadgets/luna)
  87 with [USB3300 PHY](https://www.microchip.com/wwwproducts/en/USB3300#datasheet-toggle) (Tested max at 333MB/s with Luna on ECP5)
  88  - [[shakti/m_class/USB3]]
  89
  90 ## Basic
  91
  92 These should be easily doable with LiteX.
  93
  94 * [[shakti/m_class/UART]]
  95 * [[shakti/m_class/I2C]]
  96 * [[shakti/m_class/GPIO]]
  97 * [[shakti/m_class/SPI]]
  98 * [[shakti/m_class/QSPI]]
  99 * [[shakti/m_class/LPC]]
 100 * [[shakti/m_class/EINT]]
 101 * [[shakti/m_class/RGBTTL]] in conjunction with TI TFP410a or Chrontel converter
 102
 103 # Protocols
 104  - IMPI over i2c to talk to the BMC
 105    - [Intel Spec Sheet](https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/second-gen-interface-spec-v2.pdf)
 106    - [RaptorCS HDL](https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga/blob/master/ipmi_bt_slave.v)
 107  - Reset Vector is set Flexver address over LPC
 108    - [Whitepaper](https://www.raptorengineering.com/TALOS/documentation/flexver_intro.pdf)