22nm_PowerPI.mdwn

   1 # Introduction
   2
   3
   4 # Specs for 22/28nm SOC
   5
   6 **Overall goal: an SoC that is capable of meeting multiple markets:**
   7
   8 * Basic "Pi" style SBC role (aka POWER-Pi)
   9   - Power consumption to be **strictly** limited to under 3.5 watts
  10     so as to be passively-cooled and significantly reduce product costs,
  11     as well as increase reliability
  12 * Libre-style smartphone, tablet, netbook and chromebook products
  13   - Pine64, Purism, FairPhone, many others
  14   - 3.5 watt limit greatly simplifies portable product development,
  15     as well as increasing battery life
  16 * Baseboard Management Controller (BMC) replacement for existing BMC products
  17   - including PCIe Video Card capability after BMC Boot
  18 * Mid-end low-cost Graphics Card with reasonable 3D and VPU capabilities
  19   - This as a sub-goal of the BMC functionality (stand-alone)
  20
  21 By meeting the needs of multiple markets in a single SoC the product has
  22 broader appeal yet amortises the NREs across all of them.  This is
  23 industry-standard practice: ST Micro and ATMEL use the exact same die in
  24 up to 12-14 different products.
  25
  26 **Three different pin packages:**
  27
  28 * 400-450 pin FBGA 18mm 0.8mm and 14mm 0.6mm pitch
  29   - single 32-bit DDR3/4 interface.
  30   - Suitable for smaller products.
  31   - 0.8mm pitch is easier for low-cost China PCB manufacturing
  32   - This lesson is learned from Freescale's 19-year-LTS iMX6 SoC
  33 * 600-650 pin FBGA appx 20mm 0.6mm pitch
  34   - dual 32-bit DDR3/4 interfaces.
  35   - Suitable for 4k HD resolution screens and Graphics Card capability.
  36
  37 By re-packaging the same die in different FPGA packages it meets the
  38 needs of different markets without significant NREs.  Texas Instruments
  39 and Freescale/NXP and many other companies follow this practice.
  40
  41 **Timeframe from when funding is received:**
  42
  43 * 6-8 months for PHY negotiation and supply by IP Vendors (DDR4 is always
  44   custom-tailored by the supplier)
  45 * 6-8 months development (in parallel with PHY negotiation)
  46 * 3-4 months FPGA proof-of-concept (partial overlap with above)
  47 * 4-6 months layout development once design is frozen (partial overlap with
  48   above)
  49
  50 Total: 12-18 months development time.  **This is industry-standard**
  51
  52 **NREs:**
  53
  54 These are ballpark estimates:
  55
  56 * USD 250,000 for layout software licensing (Cadence / Synopsis / Mentor)
  57 * USD 400,000 for engineer to perform layout to GDS-II
  58 * USD 1,000,000 for (LP)DDR3/4 which includes customisation by IP vendor
  59 * USD 250,000 for Libre-licensed DDR firmware (normally closed binary)
  60 * USD 250,000 for USB3/C
  61 * USD 250,000 for HDMI PHY (includes HDCP closed firmware: DVI may be better)
  62 * USD 50,000 for PCIe PHY
  63 * USD 50,000 for RGMII Ethernet PHY
  64 * USD 50,000 for Libre-licensed PCIe firmware (normally closed binary)
  65 * USD 2,000,000 for Software and Hardware Engineers
  66 * USD 2,000,000 for 22nm Production Masks (1,000,000 for 28nm)
  67 * USD 200,000 per 22nm MPW Shuttle Service (test ASICs.  28nm is 100,000)
  68 * USD 200,000 estimated for other PHYs (UART, SD/MMC, I2C, SPI)
  69
  70 Total is around USD 7 million.
  71
  72 Note that this is a bare minimum and may require re-spins of the production
  73 masks.  A safety margin is recommended to cover at least 2 additional
  74 re-spins.  Business Operating costs bring the total realistically
  75 to around USD 12 million.
  76
  77 Production cost is expected to be around the $3.50 to $4 mark meaning
  78 that a sale price of around $12-$13 will require **1 million units**
  79 sold to recover the NREs.
  80
  81 **Even if the SoC used an off-the-shelf OpenPOWER core or a lower
  82 functionality core without GPU or VPU capability these development
  83 NREs are still required**
  84
  85 # Functionality
  86
  87  - 4 Core dual-issue LibreSOC OpenPOWER CPU
  88  - SimpleV Capability with VPU and GPU Instructions *no need for separate GPU*
  89  - IOMMU
  90  - PCIe Host Controller
  91  - PCIe Slave controller (RaptorCS wants to use LibreSOC as a Graphics Card
  92     on their TALOS-II motherboards)
  93  - BMC capability (OpenBMC / LibreBMC) - enables LibreSOC to replace the
  94    closed source existing market BMC product range, booting up large servers
  95    securely
  96  - RGB/TTL framebuffer VGA/LCD PHY from Richard Herveille, RoaLogic.
  97  - Pinmux for mapping multiple I/O functions to pins (standard fare
  98    for SoCs, to reduce pincount)
  99  - SD/MMC and eMMC
 100  - Standard "Pi / Arduino" SoC-style interfaces including UART, I2C,
 101    SPI, GPIO, PWM, EINT, AC97.
 102
 103 # Interfaces
 104
 105 ## Advanced
 106
 107  - SERDES - 10rx, 14tx
 108    - 4tx, 4rx for [OMI(DDR4](https://openpowerfoundation.org/wp-content/uploads/2018/10/Jeff-Steuchli.OpenCAPI-OPS-OMI.pdf) on top of SERDES with OpenCAPI protocol) @5GHz
 109    - 4tx, 4rx for PCIe and other CAPI devices
 110    - 3tx for HDMI (note: requires HDMI Trademark Licensing and Compliance Testing.  DVI is an alternative)
 111  - [OpenFSI](https://openpowerfoundation.org/?resource_lib=field-replaceable-unit-fru-service-interface-fsi-openfsi-specification) instead of JTAG
 112    - [Raptor HDL](https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga)
 113    - [Raptor Libsigrok](https://gitlab.raptorengineering.com/raptor-engineering-public/dsview/-/tree/master/libsigrokdecode4DSL/decoders/fsi)
 114  - USB-OTG / USB2 - [Luna USB](https://github.com/greatscottgadgets/luna)
 115 with [USB3300 PHY](https://www.microchip.com/wwwproducts/en/USB3300#datasheet-toggle) (Tested max at 333MB/s with Luna on ECP5)
 116  - [[shakti/m_class/USB3]]
 117
 118 ## Basic
 119
 120 These should be easily doable with LiteX.
 121
 122 * [[shakti/m_class/UART]]
 123 * [[shakti/m_class/I2C]]
 124 * [[shakti/m_class/GPIO]]
 125 * [[shakti/m_class/SPI]]
 126 * [[shakti/m_class/QSPI]]
 127 * [[shakti/m_class/LPC]] - BMC Management
 128 * [[shakti/m_class/EINT]]
 129 * [[shakti/m_class/PWM]]
 130 * [[shakti/m_class/RGBTTL]] in conjunction with:
 131   - TI TFP410a (DVI / HDMI)
 132   - Chrontel converter (DVI, eDP, VGA)
 133   - Solomon SSD2828 (MIP)
 134   - TI SN75LVDS83b (LVDS)
 135
 136 # Protocols
 137  - IMPI over i2c to talk to the BMC
 138    - [Intel Spec Sheet](https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/second-gen-interface-spec-v2.pdf)
 139    - [RaptorCS HDL](https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga/blob/master/ipmi_bt_slave.v)
 140  - Reset Vector is set Flexver address over LPC
 141    - [Whitepaper](https://www.raptorengineering.com/TALOS/documentation/flexver_intro.pdf)
 142
 143 # Notes
 144
 145 * closed source BMC when web-enabled is a high value hacking target
 146
 147