22nm_PowerPI.mdwn

   1 # Introduction
   2
   3 This is a page describing a proposed mass-volume SoC (minimum 1 million
   4 units for commercial viability).  It outlines:
   5
   6 * the NREs involved (realistically USD $12m)
   7 * proposes a fair market price (around $12-13)
   8 * estimates a manufacturing cost (around $3.50 to $4)
   9 * realistic industry-standard timescales (12-18 months).
  10
  11 Several ways in which this may be achieved include:
  12
  13 * VC investors (typically requires multiple LOIs and customer committments)
  14 * European Union Grants (such as [SiPearl](https://www.eenewsanalog.com/news/european-processor-startup-gets-eu62-million-kickstart-grant) and the [EPI](https://www.european-processor-initiative.eu/dissemination-material/epi-consortium-members-list/) )
  15 * Direct OEM / Customer investment: pre-orders in effect
  16
  17 With enough direct customers, VC funding may not even be needed.  This is
  18 a preferred route that is not unreasonable and has been achieved before
  19 in the Silicon Industry.
  20
  21 # Specs for 22/28nm SOC
  22
  23 **Overall goal: an SoC that is capable of meeting multiple markets:**
  24
  25 * Basic "Pi" style SBC role (aka POWER-Pi)
  26   - Power consumption to be **strictly** limited to under 3.5 watts
  27     so as to be passively-cooled and significantly reduce product costs,
  28     as well as increase reliability
  29 * Libre-style smartphone, tablet, netbook and chromebook products
  30   - Pine64, Purism, FairPhone, many others
  31   - 3.5 watt limit greatly simplifies portable product development,
  32     as well as increasing battery life
  33 * Baseboard Management Controller (BMC) replacement for existing BMC products
  34   - including PCIe Video Card capability after BMC Boot
  35 * Mid-end low-cost Graphics Card with reasonable 3D and VPU capabilities
  36   - This as a sub-goal of the BMC functionality (stand-alone)
  37
  38 By meeting the needs of multiple markets in a single SoC the product has
  39 broader appeal yet amortises the NREs across all of them.  This is
  40 industry-standard practice: ST Micro and ATMEL use the exact same die in
  41 up to 12-14 different products.
  42
  43 **Three different pin packages:**
  44
  45 * 400-450 pin FBGA 18mm 0.8mm and 14mm 0.6mm pitch
  46   - single 32-bit DDR3/4 interface.
  47   - Suitable for smaller products.
  48   - 0.8mm pitch is easier for low-cost China PCB manufacturing
  49   - This lesson is learned from Freescale's 19-year-LTS iMX6 SoC
  50 * 600-650 pin FBGA appx 20mm 0.6mm pitch
  51   - dual 32-bit DDR3/4 interfaces.
  52   - Suitable for 4k HD resolution screens and Graphics Card capability.
  53
  54 By re-packaging the same die in different FPGA packages it meets the
  55 needs of different markets without significant NREs.  Texas Instruments
  56 and Freescale/NXP and many other companies follow this practice.
  57
  58 **Timeframe from when funding is received:**
  59
  60 * 6-8 months for PHY negotiation and supply by IP Vendors (DDR4 is always
  61   custom-tailored by the supplier)
  62 * 6-8 months development (in parallel with PHY negotiation)
  63 * 3-4 months FPGA proof-of-concept (partial overlap with above)
  64 * 4-6 months layout development once design is frozen (partial overlap with
  65   above)
  66
  67 Total: 12-18 months development time.  **This is industry-standard**
  68
  69 **NREs:**
  70
  71 These are ballpark estimates:
  72
  73 * USD 250,000 for layout software licensing (Cadence / Synopsis / Mentor)
  74 * USD 400,000 for engineer to perform layout to GDS-II
  75 * USD 1,000,000 for (LP)DDR3/4 which includes customisation by IP vendor
  76 * USD 250,000 for Libre-licensed DDR firmware (normally closed binary)
  77 * USD 250,000 for USB3/C
  78 * USD 250,000 for HDMI PHY (includes HDCP closed firmware: DVI may be better)
  79 * USD 50,000 for PCIe PHY
  80 * USD 50,000 for RGMII Ethernet PHY
  81 * USD 50,000 for Libre-licensed PCIe firmware (normally closed binary)
  82 * USD 2,000,000 for Software and Hardware Engineers
  83 * USD 2,000,000 for 22nm Production Masks (1,000,000 for 28nm)
  84 * USD 200,000 per 22nm MPW Shuttle Service (test ASICs.  28nm is 100,000)
  85 * USD 200,000 estimated for other PHYs (UART, SD/MMC, I2C, SPI)
  86
  87 Total is around USD 7 million.
  88
  89 Note that this is a bare minimum and may require re-spins of the production
  90 masks.  A safety margin is recommended to cover at least 2 additional
  91 re-spins.  Business Operating costs bring the total realistically
  92 to around USD 12 million.
  93
  94 Production cost is expected to be around the $3.50 to $4 mark meaning
  95 that a sale price of around $12-$13 will require **1 million units**
  96 sold to recover the NREs.
  97
  98 **Even if the SoC used an off-the-shelf OpenPOWER core or a lower
  99 functionality core without GPU or VPU capability these development
 100 NREs are still required**
 101
 102 # Functionality
 103
 104  - 4 Core dual-issue LibreSOC OpenPOWER CPU
 105  - SimpleV Capability with VPU and GPU Instructions *no need for separate GPU*
 106  - IOMMU
 107  - PCIe Host Controller
 108  - PCIe Slave controller (RaptorCS wants to use LibreSOC as a Graphics Card
 109     on their TALOS-II motherboards)
 110  - BMC capability (OpenBMC / LibreBMC) - enables LibreSOC to replace the
 111    closed source existing market BMC product range, booting up large servers
 112    securely
 113  - RGB/TTL framebuffer VGA/LCD PHY from Richard Herveille, RoaLogic.
 114  - Pinmux for mapping multiple I/O functions to pins (standard fare
 115    for SoCs, to reduce pincount)
 116  - SD/MMC and eMMC
 117  - Standard "Pi / Arduino" SoC-style interfaces including UART, I2C,
 118    SPI, GPIO, PWM, EINT, AC97.
 119
 120 # Interfaces
 121
 122 ## Advanced
 123
 124  - SERDES - 10rx, 14tx
 125    - 4tx, 4rx for [OMI(DDR4](https://openpowerfoundation.org/wp-content/uploads/2018/10/Jeff-Steuchli.OpenCAPI-OPS-OMI.pdf) on top of SERDES with OpenCAPI protocol) @5GHz
 126    - 4tx, 4rx for PCIe and other CAPI devices
 127    - 3tx for HDMI (note: requires HDMI Trademark Licensing and Compliance Testing.  DVI is an alternative)
 128  - [OpenFSI](https://openpowerfoundation.org/?resource_lib=field-replaceable-unit-fru-service-interface-fsi-openfsi-specification) instead of JTAG
 129    - [Raptor HDL](https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga)
 130    - [Raptor Libsigrok](https://gitlab.raptorengineering.com/raptor-engineering-public/dsview/-/tree/master/libsigrokdecode4DSL/decoders/fsi)
 131  - USB-OTG / USB2 - [Luna USB](https://github.com/greatscottgadgets/luna)
 132 with [USB3300 PHY](https://www.microchip.com/wwwproducts/en/USB3300#datasheet-toggle) (Tested max at 333MB/s with Luna on ECP5)
 133  - [[shakti/m_class/USB3]]
 134
 135 ## Basic
 136
 137 These should be easily doable with LiteX.
 138
 139 * [[shakti/m_class/UART]]
 140 * [[shakti/m_class/I2C]]
 141 * [[shakti/m_class/GPIO]]
 142 * [[shakti/m_class/SPI]]
 143 * [[shakti/m_class/QSPI]]
 144 * [[shakti/m_class/LPC]] - BMC Management
 145 * [[shakti/m_class/EINT]]
 146 * [[shakti/m_class/PWM]]
 147 * [[shakti/m_class/RGBTTL]] in conjunction with:
 148   - TI TFP410a (DVI / HDMI)
 149   - Chrontel converter (DVI, eDP, VGA)
 150   - Solomon SSD2828 (MIP)
 151   - TI SN75LVDS83b (LVDS)
 152
 153 # Protocols
 154  - IMPI over i2c to talk to the BMC
 155    - [Intel Spec Sheet](https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/second-gen-interface-spec-v2.pdf)
 156    - [RaptorCS HDL](https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga/blob/master/ipmi_bt_slave.v)
 157  - Reset Vector is set Flexver address over LPC
 158    - [Whitepaper](https://www.raptorengineering.com/TALOS/documentation/flexver_intro.pdf)
 159
 160 # Notes
 161
 162 * closed source BMC when web-enabled is a high value hacking target
 163
 164