22nm_PowerPI.mdwn

   1 # Specs for 22/28nm SOC
   2
   3 **Overall goal: an SoC that is capable of meeting multiple markets:**
   4
   5 * Basic "Pi" style SBC role (aka POWER-Pi)
   6   - Power consumption to be **strictly** limited to under 3.5 watts
   7     so as to be passively-cooled and significantly reduce product costs,
   8     as well as increase reliability
   9 * Libre-style smartphone, tablet, netbook and chromebook products
  10   - Pine64, Purism, FairPhone, many others
  11   - 3.5 watt limit greatly simplifies portable product development,
  12     as well as increasing battery life
  13 * Baseboard Management Controller (BMC) replacement for ASpeed products
  14   - including PCIe Video Card capability after BMC Boot
  15 * Mid-end low-cost Graphics Card with reasonable 3D and VPU capabilities
  16   - This as a sub-goal of the BMC functionality (stand-alone)
  17
  18 By meeting the needs of multiple markets in a single SoC the product has
  19 broader appeal yet amortises the NREs across all of them.  This is
  20 industry-standard practice: ST Micro and ATMEL use the exact same die in
  21 up to 12-14 different products.
  22
  23 Three different pin packages:
  24
  25 * 400-450 pin FBGA 18mm 0.8mm and 14mm 0.6mm pitch,
  26   single 32-bit DDR3/4 interface.  Suitable for smaller products:
  27   0.8mm pitch is easier for low-cost China PCB manufacturing.
  28 * 600-650 pin FPGA appx 20mm 0.6mm pitch, dual 32-bit DDR3/4 interfaces.
  29   Suitable for 4k HD resolution screens and Graphics Card capability.
  30
  31 **Timeframe from when funding is received:**
  32
  33 * 6-8 months for PHY negotiation and supply by IP Vendors (DDR4 is always
  34   custom-tailored by the supplier)
  35 * 6-8 months development (in parallel with PHY negotiation)
  36 * 3-4 months FPGA proof-of-concept (partial overlap with above)
  37 * 4-6 months layout development once design is frozen (partial overlap with
  38   above)
  39
  40 Total: 12-18 months development time.  **This is industry-standard**
  41
  42 **NREs:**
  43
  44 These are ballpark estimates:
  45
  46 * USD 250,000 for layout software licensing (Cadence / Synopsis / Mentor)
  47 * USD 400,000 for engineer to perform layout to GDS-II
  48 * USD 1,000,000 for (LP)DDR3/4 which includes customisation by IP vendor
  49 * USD 250,000 for Libre-licensed DDR firmware (normally closed binary)
  50 * USD 250,000 for USB3/C
  51 * USD 250,000 for HDMI PHY (includes HDCP closed firmware: DVI may be better)
  52 * USD 50,000 for PCIe PHY
  53 * USD 50,000 for RGMII Ethernet PHY
  54 * USD 50,000 for Libre-licensed PCIe firmware (normally closed binary)
  55 * USD 2,000,000 for Engineers
  56 * USD 2,000,000 for 22nm Production Masks (1,000,000 for 28nm)
  57 * USD 200,000 per 22nm MPW Shuttle Service (test ASICs.  28nm is 100,000)
  58 * USD 200,000 estimated for other PHYs (UART, SD/MMC, I2C, SPI)
  59
  60 Total is around USD 7 million.
  61
  62 Note that this is a bare minimum and may require re-spins of the production
  63 masks.  A safety margin is recommended to cover at least 2 additional
  64 re-spins.  Business Operating costs bring the total realistically
  65 to around USD 12 million.
  66
  67 Production cost is expected to be around the $3.50 to $4 mark meaning
  68 that a sale price of around $12-$13 will require **1 million units**
  69 sold to recover the NREs.
  70
  71 **Even if the SoC used an off-the-shelf OpenPOWER core these development
  72 NREs are still required**
  73
  74 # Functionality
  75
  76  - 4 Core dual-issue LibreSOC OpenPOWER CPU
  77  - SimpleV Capability with VPU and GPU Instructions *no need for separate GPU*
  78  - IOMMU
  79  - PCIe Host Controller
  80  - PCIe Slave controller (RaptorCS wants to use LibreSOC as a Graphics Card
  81     on their TALOS-II motherboards)
  82  - BMC capability (OpenBMC / LibreBMC) - enables LibreSOC to replace the
  83    closed source ASpeed BMC product range, booting up large servers
  84    securely
  85  - RGB/TTL framebuffer VGA/LCD PHY from Richard Herveille, RoaLogic.
  86  - Pinmux for mapping multiple I/O functions to pins (standard fare
  87    for SoCs, to reduce pincount)
  88  - SD/MMC and eMMC
  89  - Standard "Pi / Arduino" SoC-style interfaces including UART, I2C,
  90    SPI, GPIO, PWM, EINT, AC97.
  91
  92 # Interfaces
  93
  94 ## Advanced
  95
  96  - SERDES - 10rx, 14tx
  97    - 4tx, 4rx for [OMI(DDR4](https://openpowerfoundation.org/wp-content/uploads/2018/10/Jeff-Steuchli.OpenCAPI-OPS-OMI.pdf) on top of SERDES with OpenCAPI protocol) @5GHz
  98    - 4tx, 4rx for PCIe and other CAPI devices
  99    - 3tx for HDMI (note: requires HDMI Trademark Licensing and Compliance Testing.  DVI is an alternative)
 100  - [OpenFSI](https://openpowerfoundation.org/?resource_lib=field-replaceable-unit-fru-service-interface-fsi-openfsi-specification) instead of JTAG
 101    - [Raptor HDL](https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga)
 102    - [Raptor Libsigrok](https://gitlab.raptorengineering.com/raptor-engineering-public/dsview/-/tree/master/libsigrokdecode4DSL/decoders/fsi)
 103  - USB-OTG / USB2 - [Luna USB](https://github.com/greatscottgadgets/luna)
 104 with [USB3300 PHY](https://www.microchip.com/wwwproducts/en/USB3300#datasheet-toggle) (Tested max at 333MB/s with Luna on ECP5)
 105  - [[shakti/m_class/USB3]]
 106
 107 ## Basic
 108
 109 These should be easily doable with LiteX.
 110
 111 * [[shakti/m_class/UART]]
 112 * [[shakti/m_class/I2C]]
 113 * [[shakti/m_class/GPIO]]
 114 * [[shakti/m_class/SPI]]
 115 * [[shakti/m_class/QSPI]]
 116 * [[shakti/m_class/LPC]] - BMC Management
 117 * [[shakti/m_class/EINT]]
 118 * [[shakti/m_class/PWM]]
 119 * [[shakti/m_class/RGBTTL]] in conjunction with:
 120   - TI TFP410a (DVI / HDMI)
 121   - Chrontel converter (DVI, eDP, VGA)
 122   - Solomon SSD2828 (MIP)
 123   - TI SN75LVDS83b (LVDS)
 124
 125 # Protocols
 126  - IMPI over i2c to talk to the BMC
 127    - [Intel Spec Sheet](https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/second-gen-interface-spec-v2.pdf)
 128    - [RaptorCS HDL](https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga/blob/master/ipmi_bt_slave.v)
 129  - Reset Vector is set Flexver address over LPC
 130    - [Whitepaper](https://www.raptorengineering.com/TALOS/documentation/flexver_intro.pdf)