22nm_PowerPI.mdwn

   1 # Introduction
   2
   3 This is a page describing a proposed mass-volume SoC.  It outlines:
   4
   5 * the NREs involved (realistically USD $7m, with headroom up to $12m preferred)
   6 * proposes a fair market price (around $12-13)
   7 * estimates a manufacturing cost (around $3.50 to $4)
   8 * realistic industry-standard timescales (12-18 months).
   9
  10 On that basis it indicates that commercial viability is possible if the
  11 quantities ordered are over 1 million units.
  12 Several ways in which the NREs may be covered in order to be viable include:
  13
  14 * VC investors (typically requires multiple LOIs and customer committments)
  15 * European Union Grants (such as [SiPearl](https://www.eenewsanalog.com/news/european-processor-startup-gets-eu62-million-kickstart-grant) and the [EPI](https://www.european-processor-initiative.eu/dissemination-material/epi-consortium-members-list/) )
  16 * Direct OEM / Customer investment (pre-orders, in effect)
  17
  18 With enough direct customers, VC funding may not even be needed.  This is
  19 a preferred route that is not unreasonable and has been achieved before
  20 in the Silicon Industry.
  21
  22 # Specs for 22/28nm SOC
  23
  24 **Overall goal: an SoC that is capable of meeting multiple markets:**
  25
  26 * Basic "Pi" style SBC role (aka POWER-Pi)
  27   - Power consumption to be **strictly** limited to under 3.5 watts
  28     so as to be passively-cooled and significantly reduce OEM product costs,
  29     as well as increase reliability
  30 * Libre-style smartphone, tablet, netbook and chromebook products
  31   - Pine64, Purism, FairPhone, many others
  32   - 3.5 watt limit greatly simplifies portable product development,
  33     as well as increasing battery life
  34 * Baseboard Management Controller (BMC) replacement for existing BMC products
  35   - including PCIe Video Card capability after BMC Boot
  36 * Mid-end low-cost Graphics Card with reasonable 3D and VPU capabilities
  37   - This as a sub-goal of the BMC functionality (stand-alone)
  38
  39 By meeting the needs of multiple markets in a single SoC the product has
  40 broader appeal yet amortises the NREs across all of them.  This is
  41 industry-standard practice: ST Micro and ATMEL use the exact same die in
  42 up to 12-14 different products.
  43
  44 **Three different pin packages:**
  45
  46 * 400-450 pin FBGA 18mm 0.8mm and 14mm 0.6mm pitch
  47   - single 32-bit DDR3/4 interface (appx 120 pins incl. VSS/VDD)
  48   - Suitable for smaller products.
  49   - 0.8mm pitch is easier for low-cost China PCB manufacturing
  50   - This lesson is learned from Freescale's 19-year-LTS iMX6 SoC
  51 * 600-650 pin FBGA appx 20mm 0.6mm pitch
  52   - dual 32-bit DDR3/4 interfaces.
  53   - Suitable for 4k HD resolution screens and Graphics Card capability.
  54
  55 By re-packaging the same die in different FPGA packages it meets the
  56 needs of different markets without significant NREs.  Texas Instruments
  57 and Freescale/NXP and many other companies follow this practice.
  58
  59 **Timeframe from when funding is received:**
  60
  61 * 6-8 months for PHY negotiation and supply by IP Vendors (DDR4 is always
  62   custom-tailored by the supplier)
  63 * 6-8 months development (in parallel with PHY negotiation)
  64 * 3-4 months FPGA proof-of-concept (partial overlap with above)
  65 * 4-6 months layout development once design is frozen (partial overlap with
  66   above)
  67
  68 Total: 12-18 months development time.  **This is industry-standard**
  69
  70 **NREs:**
  71
  72 These are ballpark estimates:
  73
  74 * USD 250,000 for layout software licensing (Cadence / Synopsis / Mentor)
  75 * USD 400,000 for engineer to perform layout to GDS-II
  76 * USD 1,000,000 for (LP)DDR3/4 which includes customisation by IP vendor
  77 * USD 250,000 for Libre-licensed DDR firmware (normally closed binary)
  78 * USD 250,000 for USB3/C
  79 * USD 250,000 for HDMI PHY (includes HDCP closed firmware: DVI may be better)
  80 * USD 50,000 for PCIe PHY
  81 * USD 50,000 for RGMII Ethernet PHY
  82 * USD 50,000 for Libre-licensed PCIe firmware (normally closed binary)
  83 * USD 2,000,000 for Software and Hardware Engineers
  84 * USD 2,000,000 for 22nm Production Masks (1,000,000 for 28nm)
  85 * USD 200,000 per 22nm MPW Shuttle Service (test ASICs.  28nm is 100,000)
  86 * USD 200,000 estimated for other PHYs (UART, SD/MMC, I2C, SPI)
  87
  88 Total is around USD 7 million.
  89
  90 Note that this is a bare minimum and may require re-spins of the production
  91 masks.  A safety margin is recommended to cover at least 2 additional
  92 re-spins.  Business Operating costs bring the total realistically
  93 to around USD 12 million.
  94
  95 Production cost is expected to be around the $3.50 to $4 mark meaning
  96 that a sale price of around $12-$13 will require **1 million units**
  97 sold to recover the NREs.
  98
  99 **Even if the SoC used an off-the-shelf OpenPOWER core or a lower
 100 functionality core without GPU or VPU capability these development
 101 NREs are still required**
 102
 103 # Functionality
 104
 105  - 4 Core SMP dual-issue LibreSOC OpenPOWER CPU
 106  - SimpleV Capability with VPU and GPU Instructions *no need for separate GPU*
 107  - IOMMU
 108  - PCIe Host Controller
 109  - PCIe Slave controller (RaptorCS wants to use LibreSOC as a Graphics Card
 110     on their TALOS-II motherboards)
 111  - BMC capability (OpenBMC / LibreBMC) - enables LibreSOC to replace the
 112    closed source existing market BMC product range, booting up large servers
 113    securely
 114  - RGB/TTL framebuffer VGA/LCD PHY from Richard Herveille, RoaLogic.
 115  - Pinmux for mapping multiple I/O functions to pins (standard fare
 116    for SoCs, to reduce pincount)
 117  - SD/MMC and eMMC
 118  - Standard "Pi / Arduino" SoC-style interfaces including UART, I2C,
 119    SPI, GPIO, PWM, EINT, AC97.
 120
 121 The "PI / Arduino" style interfaces are provided so as to be pin-comoatibke with the existing "Shield" 3rd party producy markets.
 122
 123 # Interfaces
 124
 125 Much of the advanced section is "under consideration" because there are proprietary firmware issues involved as well as high power consumption and high costs involved.  OpenCAPI for example would, in 22nm, at 25 ghz, be an enormous power draw (IBM used 14nm for the POWER9 25ghz SERDES)
 126
 127 HDCP is present in HDMI, as well as being optional in eDP and by extension USB-C as well.  Licensing of any of these Controllers therefore introduces the risk of closed firmware which will be viewed unfavourably by the educational markets, libre/open supporters and advocates, as well as cause Customer Support issues and introduce security vulnerabilities that *cannot be fixed or evaluated*.
 128
 129 Great care therefore needs to be taken in selecting the advanced interfaces.
 130
 131 ## Advanced
 132
 133  - SERDES - 10rx, 14tx
 134    - 4tx, 4rx for [OMI(DDR4](https://openpowerfoundation.org/wp-content/uploads/2018/10/Jeff-Steuchli.OpenCAPI-OPS-OMI.pdf) on top of SERDES with OpenCAPI protocol) @25GHz
 135    - 4tx, 4rx for PCIe and other CAPI devices
 136    - 3tx for HDMI (note: requires HDMI Trademark Licensing and Compliance Testing.  DVI is an alternative)
 137  - USB-OTG / USB2 - [Luna USB](https://github.com/greatscottgadgets/luna)
 138 with [USB3300 PHY](https://www.microchip.com/wwwproducts/en/USB3300#datasheet-toggle) (Tested max at 333MB/s with Luna on ECP5)
 139  - [[shakti/m_class/USB3]]
 140
 141 ## Basic
 142
 143  - [OpenFSI](https://openpowerfoundation.org/?resource_lib=field-replaceable-unit-fru-service-interface-fsi-openfsi-specification) instead of / as well as JTAG
 144   - [Raptor HDL](https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga)
 145   - [Raptor Libsigrok](https://gitlab.raptorengineering.com/raptor-engineering-public/dsview/-/tree/master/libsigrokdecode4DSL/decoders/fsi)
 146
 147 These should be easily doable with LiteX.
 148
 149 * [[shakti/m_class/UART]]
 150 * [[shakti/m_class/JTAG]]
 151 * [[shakti/m_class/I2C]]
 152 * [[shakti/m_class/GPIO]]
 153 * [[shakti/m_class/SPI]]
 154 * [[shakti/m_class/QSPI]]
 155 * [[shakti/m_class/LPC]] - BMC Management
 156 * [[shakti/m_class/EINT]]
 157 * [[shakti/m_class/PWM]]
 158 * [[shakti/m_class/RGBTTL]] in conjunction with:
 159   - TI TFP410a (DVI / HDMI)
 160   - Chrontel converter (DVI, eDP, VGA)
 161   - Solomon SSD2828 (MIP)
 162   - TI SN75LVDS83b (LVDS)
 163
 164 # Protocols
 165  - IMPI over i2c to talk to the BMC
 166    - [Intel Spec Sheet](https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/second-gen-interface-spec-v2.pdf)
 167    - [RaptorCS HDL](https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga/blob/master/ipmi_bt_slave.v)
 168  - Reset Vector is set Flexver address over LPC
 169    - [Whitepaper](https://www.raptorengineering.com/TALOS/documentation/flexver_intro.pdf)
 170
 171 # Notes
 172
 173 * closed source BMC when web-enabled is a high value hacking target
 174
 175