3d_gpu/architecture/memory_and_cache.mdwn

   1 # 180nm Test ASIC
   2
   3 This is a single-core, non-SMP, no analog PLLs, no clock-gating, test ASIC,
   4 expected to run at one-to-one from an external 24 mhz to 100 mhz clock.
   5
   6 The requirements are therefore **radically different** from the next
   7 roadmap ASIC.
   8
   9 Walkthrough video: <https://youtu.be/6Yiyw4abJpE>
  10
  11 Basic diagram:
  12
  13 [[!img 180nm_single_core_test_asic_memlayout.svg size="825x"]]
  14
  15 * Eight LD/ST Function Units with 2 ports each (one for aligned,
  16   one for misaligned), each connecting to one of a pair of L0
  17   Cache/Buffers.  Addr[4] determines which L0 Cache/Buffer to
  18   connect to.
  19
  20 * A L0 Cache/Buffer with dual 8x 128-bit-wide entries and
  21   a single-clock, single-path outgoing read **or** write protocol,
  22   with 8 pairs of (individual, non-multiplexed) incoming 128-bit entries
  23   where each pair is hard-required to have the same top bits (12-48).
  24   The left port has address bit 4 set to zero, the right port to 1.
  25
  26 * The L0 Cache/Buffer connects to a pair of 128-bit data paths
  27   to a standard non-SMP-aware L1 cache.  The data in and out
  28   on each port is again read **or** write, 128-bit-wide.
  29
  30 * A pair of Wishbone "funnels" take the 128-bit requests, which include
  31   byte-level access lines, and *if needed* create a pair of 64-bit
  32   Wishbone-compliant requests.  "If needed", because if the lower
  33   half (or upper half) byte-level access lines are not set, then
  34   that indicates a 64-bit request, and thus only one request is needed.
  35   Only when byte-access lines in both upper and lower halves are set
  36   will two requests be needed
  37
  38 * Standard Wishbone 64-bit Bus.  This is where
  39   [Enjoy-Digital Litex](https://github.com/enjoy-digital/litex)
  40   code takes over, and connect to peripherals and testing infrastructure.
  41
  42 * Memory is the silicon-proven OpenCores [[SDRAM|sdram]] interface,
  43   and it is Wishbone compliant.
  44
  45 ## Memory Interface Required by LDSTComputationalUnit
  46
  47 See <https://bugs.libre-soc.org/show_bug.cgi?id=216#c26>.  Other signals
  48 (type of LD/ST: atomic or I/O, type of exception) left out for brevity
  49
  50 Common to LD/ST:
  51
  52 * out: busy
  53 * in: is_ld
  54 * in: address
  55 * in: len (1/2/4/8)
  56 * in: go_addr
  57 * in: go_die
  58 * out: addr_ok (no exception will occur)
  59 * out: addr_exc (exception type)
  60
  61 LD:
  62
  63 * in: is_ld
  64 * out: ld_data
  65 * out: ld_data_ok (to be raised for 1 cycle)
  66
  67 ST:
  68
  69 * in: is_st
  70 * in: st_data
  71 * in: go_st (raised for 1 cycle, must complete)
  72
  73 Source: PortInterface
  74
  75 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/experiment/l0_cache.py;h=22168267b64d557ff3cc61c597505188bc2985db;hb=HEAD>
  76
  77 ## Alternative Design Idea
  78
  79 [[alternative-design-idea]]
  80
  81 # 28-45nm Quad-Core SoC
  82
  83 This is full SMP, requires analog PLLs, clock gating, full SMP
  84 L1 and L2 cache coherency and atomic coherency.
  85
  86 ## Memory
  87
  88 TODO
  89
  90 ## Cache
  91
  92 TODO
  93
  94