3d_gpu/isa_to_virtual_regs.mdwn

   1 # Lookup table for Virtual Registers including renaming
   2
   3 Links
   4
   5 * <https://groups.google.com/g/comp.arch/c/vdgvrYGoxTM/m/KerzlHs0BgAJ>
   6 * <https://bugs.libre-soc.org/show_bug.cgi?id=352>
   7
   8 [[!img isa_to_virtual_regs_table.png size="800x390"]]
   9
  10 Explanation:
  11
  12 * ISA reg numbers are in rows
  13 * Virtual (including renamed) reg numbers are in columns
  14 * from both the bottom *and* the right are multi-issue (unary) "Set1,
  15   Set2" signals
  16 * where these cross they are ANDed to set a Latch in a given cell
  17   - at no time will there be more than one cell set per row
  18   - OR per column
  19 * there being only one per column a "reset" signal can be per column
  20 * for regfile port "lookup" the per-column Set1/Set2 wires may be re-used
  21   - they may be binary or unary as preferred
  22   - read and write ports are all numbered
  23 * a "request virtual-to-real regfile port redirection" signal is along
  24   the bottom
  25   - this is ANDed with the Latch
  26   - that is MUXed with the per-column Set1/Set2 wires
  27   - ANDs which accumulate in Great Big ORs fire per-row outputs
  28
  29 in this way any "virtual" read or write request to a register file port
  30 may be translated to a "real" request.  the actual regfile data transfers
  31 on respective associated broadcast buses are external and do not need
  32 routing through this Matrix: the Matrix simply provides name translation,
  33 nothing else.
  34
  35 note that if regfile port IDs are encoded in binary, an entire column
  36 can light up like a Mythbusters Christmas tree with XOR gates unless
  37 the EN is carefully arranged.