3d_gpu/simple_core.mdwn

   1 # Non-production Simple POWER9 Core
   2
   3 the simple core is taking shape as a combination of all the pipelines,
   4 connected to the (5) types of register files.  all unit tests that
   5 have been developed to test *individual* pipelines have been borrowed
   6 through inheritance, to run against the register files, this time.
   7 you can try it out as:
   8
   9     python3 soc/simple/test/test_core.py
  10
  11 core.py is *very* simple.  its execution model is as follows:
  12
  13 * receive instruction
  14 * decode instruction
  15 * identify through bitmasking which pipeline can handle it
  16 * enable *only* the MultiCompUnit managing that pipeline
  17 * wait for it to indicate that it is not busy (this includes regfile writing)
  18 * move on to the next instruction.
  19
  20 each MultiCompUnit, of which there are currently five connected up (ALU,
  21 Logical, ShiftRot, CR, Branch), has a number of "operand in" and "result
  22 out" ports.  the register files have been *deliberately* spec'd to
  23 match one-for-one the maximum number of ports of each regfile type needed.
  24
  25 therefore, for example: whilst no other MCU needs INT 2W (2 write ports),
  26 LDSTCompUnit *does* need 2 write ports and consequently the INT regfile
  27 has been allocated 2W.  another example: CR requires *three* read ports
  28 *and* the "full" (32-bit) CR, and consequently the CR regfile is 4R
  29 (1 full, 3 4-bit).
  30
  31 this dramatically simplifies the code needed to connect up the MCUs to
  32 the Regfiles, because the port allocations (resource contention aside)
  33 is one-to-one.  the majority of the code in core.py (at present) involves
  34 reorganising [regspecs]([3d_gpu/architecture/regspecs) into a
  35 dictionary-of-dictionaries-of-lists.  the structure is:
  36
  37 * first dictionary key is the register file TYPE (INT, CR, SPRs)
  38 * second dictionary key is the register port NAME (cr0, ra, rb, XER_so)
  39 * list contains the *Function Unit* and operand/result read/write port
  40
  41 that list (on a per-file, per-regname basis) therefore contains *all*
  42 Function Units that wish to contend for that register file port, and,
  43 consequently, it is a simple matter of:
  44
  45 * A. creating a PriorityPicker to select one and *ONLY* one Function
  46   Unit that is permitted to access that port at any one time
  47 * B. creating a Broadcast Bus (fan-in in the case of write, fan-out in
  48   the case of read) connecting regfile port to Function Unit port.
  49
  50
  51 # Next phases of development
  52
  53 the next phases will involve:
  54
  55 * adding in LDSTCompUnit
  56 * adding in minerva wishbone L1 I-Cache code (including bypass mode)
  57 * including the pre-written scoreboard "Instruction Queue" code
  58 * linking up NIA to the IQ, to fetch instructions and pass them to the decoder.
  59
  60 at that point we will have an actual core that is capable of executing
  61 instructions on its own.  further code-morphs can then take place including
  62 adding in the [[architecture/6600scoreboard]].
  63
  64 # Links
  65
  66 * <https://bugs.libre-soc.org/show_bug.cgi?id=346>
  67 * <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/007828.html>