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[libreriscv.git] / 45nm_Fall2022.mdwn
1 # Specs for 2022 SOC
2
3 ## Applications
4
5 - We are providing open source drivers for the GPU,
6 hopefully completed by Fall 2022.
7 - Given that POWER CPUs do not have GPUs, RaptorCS
8 would like the LibreSOC to be able function as a
9 GPU in PCIE slave mode.
10 - Lastly, RaptorCS would like to manufacture single
11 board computers.
12
13 ## Devices
14 - 4 Core POWER CPU
15 - SimpleV GPU
16 - PCIE Slave controller(RaptorCS wants to use LibreSOC as a GPU on their POWER mob0so
17 - IOMMU
18 - Coherent Accelerator Processor Proxy (CAPP) functional unit
19 - PCIE host Controller
20
21 ## Interfaces
22
23 ### Advanced
24
25 - SERDES - 10rx, 14tx
26 - 4tx, 4rx for [OMI(DDR4](https://openpowerfoundation.org/wp-content/uploads/2018/10/Jeff-Steuchli.OpenCAPI-OPS-OMI.pdf) on top of SERDES with OpenCAPI protocol) @5GHz
27 - 2tx, 2rx for ethernet
28 - 4tx, 4rx for PCIE and other CAPI devices
29 - 3tx for HDMI
30 - [OpenFSI](https://openpowerfoundation.org/?resource_lib=field-replaceable-unit-fru-service-interface-fsi-openfsi-specification) instead of JTAG
31 - [Raptor HDL](https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga)
32 - [Raptor Libsigrok](https://gitlab.raptorengineering.com/raptor-engineering-public/dsview/-/tree/master/libsigrokdecode4DSL/decoders/fsi)
33 - USB 2.0 - [Luna USB](https://github.com/greatscottgadgets/luna)
34 with [USB3300 PHY](https://www.microchip.com/wwwproducts/en/USB3300#datasheet-toggle) (Tested max at 333MB/s with Luna on ECP5)
35
36 ### Basic
37
38 These should be easily doable with LiteX.
39
40 * [[shakti/m_class/UART]]
41 * [[shakti/m_class/I2C]]
42 * [[shakti/m_class/GPIO]]
43 * [[shakti/m_class/SPI]]
44 * [[shakti/m_class/QSPI]]
45 * [[shakti/m_class/LPC]]
46 * [[shakti/m_class/EINT]]
47
48 ## Protocols
49 - IPMT over i2c to talk to the BMC
50 - [Intel Spec Sheet](https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/second-gen-interface-spec-v2.pdf)
51 - [RaptorCS HDL](https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga/blob/master/ipmi_bt_slave.v)
52 - Reset Vector is set Flexver address over LPC
53 - [Whitepaper](https://www.raptorengineering.com/TALOS/documentation/flexver_intro.pdf)