Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn

   1 # Comparative analysis with Andes Packed ISA proposal
   2
   3 ## 16-bit Arithmetic
   4
   5 | Andes Mnemonic           | 16-bit Instruction        | Harmonised RVP Equivalent |
   6 | ------------------ | ------------------------- | ------------------- |
   7 | ADD16 rt, ra, rb   | Add                       | VADD (r16 <= rt,ra,rb <= r29), mm=00|
   8 | RADD16 rt, ra, rb  | Signed Halving add        | RADD (r16 <= rt,ra,rb <= r23), mm=00|
   9 | URADD16 rt, ra, rb | Unsigned Halving add      | RADD (r24 <= rt,ra,rb <= r29), mm=00|
  10 | KADD16 rt, ra, rb  | Signed Saturating add     | VADD (r16 <= rt,ra,rb <= r23), mm=01|
  11 | UKADD16 rt, ra, rb | Unsigned Saturating add   | VADD (r24 <= rt,ra,rb <= r29), mm=01|
  12 | SUB16 rt, ra, rb   | Subtract                  | VSUB (r16 <= rt,ra,rb <= r29), mm=00|
  13 | RSUB16 rt, ra, rb  | Signed Halving sub        | RSUB (r16 <= rt,ra,rb <= r23), mm=00|
  14 | URSUB16 rt, ra, rb | Unsigned Halving sub                | RSUB (r24 <= rt,ra,rb <= r29), mm=00|
  15 | KSUB16 rt, ra, rb  | Signed Saturating sub               | VSUB (r16 <= rt,ra,rb <= r23), mm=01|
  16 | UKSUB16 rt, ra, rb | Unsigned Saturating sub             | VSUB (r24 <= rt,ra,rb <= r29), mm=01|
  17 | CRAS16 rt, ra, rb  | Cross Add & Sub                     | |
  18 | RCRAS16 rt, ra, rb | Signed Halving Cross Add & Sub      | |
  19 | URCRAS16 rt, ra, rb| Unsigned Halving Cross Add & Sub    | |
  20 | KCRAS16 rt, ra, rb | Signed Saturating Cross Add & Sub   | |
  21 | UKCRAS16 rt, ra, rb| Unsigned Saturating Cross Add & Sub | |
  22 | CRSA16 rt, ra, rb  | Cross Sub & Add                     | |
  23 | RCRSA16 rt, ra, rb | Signed Halving Cross Sub & Add      | |
  24 | URCRSA16 rt, ra, rb| Unsigned Halving Cross Sub & Add    | |
  25 | KCRSA16 rt, ra, rb | Signed Saturating Cross Sub & Add   | |
  26 | UKCRSA16 rt, ra, rb| Unsigned Saturating Cross Sub & Add | |
  27
  28 ## 8-bit Arithmetic
  29
  30 | Andes Mnemonic           | 8-bit Instruction        | Harmonised RVP Equivalent |
  31 | ------------------ | ------------------------- | ------------------- |
  32 | ADD8 rt, ra, rb    | Add                       | VADD (r2 <= rt,ra,rb <= r15), mm=00 |
  33 | RADD8 rt, ra, rb   | Signed Halving add        | RADD (r2 <= rt,ra,rb <= r7), mm=00 |
  34 | URADD8 rt, ra, rb  | Unsigned Halving add      | RADD (r8 <= rt,ra,rb <= r15), mm=00 |
  35 | KADD8 rt, ra, rb   | Signed Saturating add     | VADD (r2 <= rt,ra,rb <= r7), mm=01 |
  36 | UKADD8 rt, ra, rb  | Unsigned Saturating add   | VADD (r8 <= rt,ra,rb <= r15), mm=01 |
  37 | SUB8 rt, ra, rb    | Subtract                  | VSUB (r2 <= rt,ra,rb <= r15), mm=00 |
  38 | RSUB8 rt, ra, rb   | Signed Halving sub        | RSUB (r2 <= rt,ra,rb <= r7), mm=00 |
  39 | URSUB8 rt, ra, rb  | Unsigned Halving sub      | RSUB (r8 <= rt,ra,rb <= r15), mm=00 |
  40 | KSUB8 rt, ra, rb   | Signed Saturating sub        | VSUB (r2 <= rt,ra,rb <= r7), mm=01 |
  41 | UKSUB8 rt, ra, rb  | Unsigned Saturating sub      | VSUB (r8 <= rt,ra,rb <= r15), mm=01 |
  42
  43 ## 16-bit Shifts
  44
  45 SRA[I]16/SRL[I]16/SLL[I]16 to be mapped to VOP shift instructions in same manner as ADD16/SUB16
  46
  47 The “K” (Saturation) and “u” (Rounding) variants could be encoded using VOP’s mm field (mm=01 is saturated or rounded shift, mm=00 is standard VOP shift)
  48
  49 | Andes Mnemonic             | 16-bit Instruction         | Harmonised RVP Equivalent |
  50 | ------------------   | -------------------------  | ------------------- |
  51 | SRA16 rt, ra, rb     | Shift right arithmetic     | VSRA (r16 <= rt,ra,rb <= r29), mm=00|
  52 | SRAI16 rt, ra, im    | Shift right arithmetic imm | VSRAI (r16 <= rt,ra <= r29), mm=00|
  53 | SRA16.u rt, ra, rb   | Rounding Shift right arithmetic     | VSRA (r16 <= rt,ra,rb <= r29), mm=01|
  54 | SRAI16.u rt, ra, im  | Rounding Shift right arithmetic imm | VSRAI (r16 <= rt,ra <= r29), mm=01|
  55 | SRL16 rt, ra, rb     | Shift right logical        | VSRL (r16 <= rt,ra,rb <= r29), mm=00|
  56 | SRLI16 rt, ra, im    | Shift right logical imm    | VSRLI (r16 <= rt,ra <= r29), mm=00|
  57 | SRL16.u rt, ra, rb   | Rounding Shift right logical     | VSRL (r16 <= rt,ra,rb <= r29), mm=01|
  58 | SRLI16.u rt, ra, im  | Rounding Shift right logical imm | VSLRI (r16 <= rt,ra <= r29), mm=01|
  59 | SLL16 rt, ra, rb     | Shift left logical         | VSLL (r16 <= rt,ra,rb <= r29), mm=00|
  60 | SLLI16 rt, ra, im    | Shift left logical imm     | VSLLI (r16 <= rt,ra <= r29), mm=00|
  61 | KSLL16 rt, ra, rb    | Saturating Shift left logical       | VSLL (r16 <= rt,ra,rb <= r29), mm=01|
  62 | KSLLI16 rt, ra, im   | Saturating Shift left logical imm   | VSLLI (r16 <= rt,ra <= r29), mm=01|
  63 | KSLRA16 rt, ra, rb    | Saturating Shift left logical or Shift right arithmetic              ||
  64 | KSLRA16.u rt, ra, rb  | Saturating Shift left logical or Rounding Shift right arithmetic     ||
  65
  66
  67 ## 8-bit Shifts
  68
  69 Andes SIMD Packed ISA omits 8 bit shifts, but these can be encoded in Harmonised RVP as follows:
  70
  71 | Andes Mnemonic             | 8-bit Instruction         | Harmonised RVP Equivalent |
  72 | ------------------   | -------------------------  | ------------------- |
  73 | n/a     | Shift right arithmetic     | VSRA (r2 <= rt,ra,rb <= r15), mm=00|
  74 | n/a     | Shift right arithmetic imm | VSRAI (r2 <= rt,ra <= r15), mm=00|
  75 | n/a     | Rounding Shift right arithmetic     | VSRA (r2 <= rt,ra,rb <= r15), mm=01|
  76 | n/a     | Rounding Shift right arithmetic imm | VSRAI (r2 <= rt,ra <= r15), mm=01|
  77 | n/a     | Shift right logical        | VSRL (r2 <= rt,ra,rb <= r15), mm=00|
  78 | n/a     | Shift right logical imm    | VSRLI (r2 <= rt,ra <= r15), mm=00|
  79 | n/a     | Rounding Shift right logical     | VSRL (r2 <= rt,ra,rb <= r15), mm=01|
  80 | n/a     | Rounding Shift right logical imm | VSLRI (r2 <= rt,ra <= r15), mm=01|
  81 | n/a     | Shift left logical         | VSLL (r2 <= rt,ra,rb <= r15), mm=00|
  82 | n/a     | Shift left logical imm     | VSLLI (r2 <= rt,ra <= r15), mm=00|
  83 | n/a     | Saturating Shift left logical       | VSLL (r2 <= rt,ra,rb <= r15), mm=01|
  84 | n/a     | Saturating Shift left logical imm   | VSLLI (r2 <= rt,ra <= r15), mm=01|
  85