Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn

   1 # Comparative analysis of Andes Packed ISA proposal vs RVP Harmonised (with RV Vector spec)
   2
   3 ## Proposed vector instruction encoding
   4
   5 Register x 2 -> register operations:
   6
   7 | 31 30 29 28 27 26 | 25  | 24 23 22 21 20 | 19 18 17 16 15 | 14 | 13 12 | 11 10 9 8 7 | 6 5 4 3 2 1 0 |
   8 | ----------------- | --  | -------------- | -------------- | -- | ----- | ----------- | ------------- |
   9 | func_6            | 0   | rs2            | rs1            | 0  | mm    | rd1         | VOP opcode    |
  10
  11 Immediate + register -> register operations:
  12
  13 | 31 30 29 | 28 27 26 | 25  | 24 23 22 21 20 | 19 18 17 16 15 | 14 | 13 12 | 11 10 9 8 7 | 6 5 4 3 2 1 0 |
  14 | -------- | -------- | --  | -------------- | -------------- | -- | ----- | ----------- | ------------- |
  15 | func_3   | imm[7:5] | 1   | imm[4:0]       | rs1            | 0  | mm    | rd1         | VOP opcode    |
  16
  17 Register x 3 -> register operations:
  18
  19 | 31 30 29 28 27 | 26 25  | 24 23 22 21 20 | 19 18 17 16 15 | 14 | 13 12 | 11 10 9 8 7 | 6 5 4 3 2 1 0 |
  20 | ----------------------- | -------------- | -------------- | -- | ----- | ----------- | ------------- |
  21 | rs3            | func_2 | rs2            | rs1            | 1  | mm    | rd1         | VOP opcode    |
  22
  23 mm values:
  24 mm = 00 -> use current global saturation or rounding, no mask
  25 mm = 00 -> force saturation or rounding for this instruction only
  26 mm = 10 -> use v1 as predicate mask
  27 mm = 11 -> use ~v1 as predicate mask
  28
  29 ## Register file
  30
  31 The default Harmonised RVP GPR register file is divided into a lower bank of Vector[INT8] and an upper bank of Vector[INT16].
  32 In contrast, the Andes Packed SIMD ISA permits any GPR to be used for either INT8 or INT16 vector operations
  33
  34 | Register           | Andes ISA                              | Harmonised RVP ISA            |
  35 | ------------------ | -------------------------              | -------------------           |
  36 | v0                 | Hardwired zero                         | Hardwired zero                |
  37 | v1                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | Predicate mask                |
  38 | |  |  |
  39 | v2                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8]  |
  40 | v3                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8]  |
  41 | v4                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8]  |
  42 | v5                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8]  |
  43 | v6                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8]  |
  44 | v7                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8]  |
  45 | v8                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  46 | v9                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  47 | v10                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  48 | v11                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  49 | v12                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  50 | v13                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  51 | v14                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  52 | v15                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8]  |
  53 | |  |  |
  54 | v16                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  55 | v17                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  56 | v18                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  57 | v19                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  58 | v20                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  59 | v21                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  60 | v22                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  61 | v23                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] |
  62 | v24                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] |
  63 | v25                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] |
  64 | v26                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] |
  65 | v27                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] |
  66 | v28                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] |
  67 | v29                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] |
  68 | |  |  |
  69 | v30                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[1xSINT32] |
  70 | v31                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[1xSINT32] |
  71
  72
  73 ## 16-bit Arithmetic
  74
  75 | Andes Mnemonic           | 16-bit Instruction        | Harmonised RVP Equivalent |
  76 | ------------------ | ------------------------- | ------------------- |
  77 | ADD16 rt, ra, rb   | Add                       | VADD (v16 <= rt,ra,rb <= v29), mm=00|
  78 | RADD16 rt, ra, rb  | Signed Halving add        | RADD (v16 <= rt,ra,rb <= v23), mm=00|
  79 | URADD16 rt, ra, rb | Unsigned Halving add      | RADD (v24 <= rt,ra,rb <= v29), mm=00|
  80 | KADD16 rt, ra, rb  | Signed Saturating add     | VADD (v16 <= rt,ra,rb <= v23), mm=01|
  81 | UKADD16 rt, ra, rb | Unsigned Saturating add   | VADD (v24 <= rt,ra,rb <= v29), mm=01|
  82 | SUB16 rt, ra, rb   | Subtract                  | VSUB (v16 <= rt,ra,rb <= v29), mm=00|
  83 | RSUB16 rt, ra, rb  | Signed Halving sub        | RSUB (v16 <= rt,ra,rb <= v23), mm=00|
  84 | URSUB16 rt, ra, rb | Unsigned Halving sub                | RSUB (v24 <= rt,ra,rb <= v29), mm=00|
  85 | KSUB16 rt, ra, rb  | Signed Saturating sub               | VSUB (v16 <= rt,ra,rb <= v23), mm=01|
  86 | UKSUB16 rt, ra, rb | Unsigned Saturating sub             | VSUB (v24 <= rt,ra,rb <= v29), mm=01|
  87 | CRAS16 rt, ra, rb  | Cross Add & Sub                     | |
  88 | RCRAS16 rt, ra, rb | Signed Halving Cross Add & Sub      | |
  89 | URCRAS16 rt, ra, rb| Unsigned Halving Cross Add & Sub    | |
  90 | KCRAS16 rt, ra, rb | Signed Saturating Cross Add & Sub   | |
  91 | UKCRAS16 rt, ra, rb| Unsigned Saturating Cross Add & Sub | |
  92 | CRSA16 rt, ra, rb  | Cross Sub & Add                     | |
  93 | RCRSA16 rt, ra, rb | Signed Halving Cross Sub & Add      | |
  94 | URCRSA16 rt, ra, rb| Unsigned Halving Cross Sub & Add    | |
  95 | KCRSA16 rt, ra, rb | Signed Saturating Cross Sub & Add   | |
  96 | UKCRSA16 rt, ra, rb| Unsigned Saturating Cross Sub & Add | |
  97
  98 ## 8-bit Arithmetic
  99
 100 | Andes Mnemonic           | 8-bit Instruction        | Harmonised RVP Equivalent |
 101 | ------------------ | ------------------------- | ------------------- |
 102 | ADD8 rt, ra, rb    | Add                       | VADD (v2 <= rt,ra,rb <= v15), mm=00 |
 103 | RADD8 rt, ra, rb   | Signed Halving add        | RADD (v2 <= rt,ra,rb <= v7), mm=00 |
 104 | URADD8 rt, ra, rb  | Unsigned Halving add      | RADD (v8 <= rt,ra,rb <= v15), mm=00 |
 105 | KADD8 rt, ra, rb   | Signed Saturating add     | VADD (v2 <= rt,ra,rb <= v7), mm=01 |
 106 | UKADD8 rt, ra, rb  | Unsigned Saturating add   | VADD (v8 <= rt,ra,rb <= v15), mm=01 |
 107 | SUB8 rt, ra, rb    | Subtract                  | VSUB (v2 <= rt,ra,rb <= v15), mm=00 |
 108 | RSUB8 rt, ra, rb   | Signed Halving sub        | RSUB (v2 <= rt,ra,rb <= v7), mm=00 |
 109 | URSUB8 rt, ra, rb  | Unsigned Halving sub      | RSUB (v8 <= rt,ra,rb <= v15), mm=00 |
 110 | KSUB8 rt, ra, rb   | Signed Saturating sub        | VSUB (v2 <= rt,ra,rb <= v7), mm=01 |
 111 | UKSUB8 rt, ra, rb  | Unsigned Saturating sub      | VSUB (v8 <= rt,ra,rb <= v15), mm=01 |
 112
 113 ## 16-bit Shifts
 114
 115 SRA[I]16/SRL[I]16/SLL[I]16 to be mapped to VOP shift instructions in same manner as ADD16/SUB16
 116
 117 The “K” (Saturation) and “u” (Rounding) variants could be encoded using VOP’s mm field (mm=01 is saturated or rounded shift, mm=00 is standard VOP shift)
 118
 119 | Andes Mnemonic             | 16-bit Instruction         | Harmonised RVP Equivalent |
 120 | ------------------   | -------------------------  | ------------------- |
 121 | SRA16 rt, ra, rb     | Shift right arithmetic     | VSRA (v16 <= rt,ra,rb <= v29), mm=00|
 122 | SRAI16 rt, ra, im    | Shift right arithmetic imm | VSRAI (v16 <= rt,ra <= v29), mm=00|
 123 | SRA16.u rt, ra, rb   | Rounding Shift right arithmetic     | VSRA (v16 <= rt,ra,rb <= v29), mm=01|
 124 | SRAI16.u rt, ra, im  | Rounding Shift right arithmetic imm | VSRAI (v16 <= rt,ra <= v29), mm=01|
 125 | SRL16 rt, ra, rb     | Shift right logical        | VSRL (v16 <= rt,ra,rb <= v29), mm=00|
 126 | SRLI16 rt, ra, im    | Shift right logical imm    | VSRLI (v16 <= rt,ra <= v29), mm=00|
 127 | SRL16.u rt, ra, rb   | Rounding Shift right logical     | VSRL (v16 <= rt,ra,rb <= v29), mm=01|
 128 | SRLI16.u rt, ra, im  | Rounding Shift right logical imm | VSLRI (v16 <= rt,ra <= v29), mm=01|
 129 | SLL16 rt, ra, rb     | Shift left logical         | VSLL (v16 <= rt,ra,rb <= v29), mm=00|
 130 | SLLI16 rt, ra, im    | Shift left logical imm     | VSLLI (v16 <= rt,ra <= v29), mm=00|
 131 | KSLL16 rt, ra, rb    | Saturating Shift left logical       | VSLL (v16 <= rt,ra,rb <= v29), mm=01|
 132 | KSLLI16 rt, ra, im   | Saturating Shift left logical imm   | VSLLI (v16 <= rt,ra <= v29), mm=01|
 133 | KSLRA16 rt, ra, rb    | Saturating Shift left logical or Shift right arithmetic              ||
 134 | KSLRA16.u rt, ra, rb  | Saturating Shift left logical or Rounding Shift right arithmetic     ||
 135
 136
 137 ## 8-bit Shifts
 138
 139 Andes SIMD Packed ISA omits 8 bit shifts, but these can be encoded in Harmonised RVP as follows:
 140
 141 | Andes Mnemonic             | 8-bit Instruction         | Harmonised RVP Equivalent |
 142 | ------------------   | -------------------------  | ------------------- |
 143 | n/a     | Shift right arithmetic     | VSRA (v2 <= rt,ra,rb <= v15), mm=00|
 144 | n/a     | Shift right arithmetic imm | VSRAI (v2 <= rt,ra <= v15), mm=00|
 145 | n/a     | Rounding Shift right arithmetic     | VSRA (v2 <= rt,ra,rb <= v15), mm=01|
 146 | n/a     | Rounding Shift right arithmetic imm | VSRAI (v2 <= rt,ra <= v15), mm=01|
 147 | n/a     | Shift right logical        | VSRL (v2 <= rt,ra,rb <= v15), mm=00|
 148 | n/a     | Shift right logical imm    | VSRLI (v2 <= rt,ra <= v15), mm=00|
 149 | n/a     | Rounding Shift right logical     | VSRL (v2 <= rt,ra,rb <= v15), mm=01|
 150 | n/a     | Rounding Shift right logical imm | VSLRI (v2 <= rt,ra <= v15), mm=01|
 151 | n/a     | Shift left logical         | VSLL (v2 <= rt,ra,rb <= v15), mm=00|
 152 | n/a     | Shift left logical imm     | VSLLI (v2 <= rt,ra <= v15), mm=00|
 153 | n/a     | Saturating Shift left logical       | VSLL (v2 <= rt,ra,rb <= v15), mm=01|
 154 | n/a     | Saturating Shift left logical imm   | VSLLI (v2 <= rt,ra <= v15), mm=01|
 155
 156 ## 16-bit Comparison instructions
 157
 158 | Andes Mnemonic           | 16-bit Instruction        | Harmonised RVP Equivalent |
 159 | ------------------   | ------------------------- | ------------------- |
 160 | CMPEQ16 rt, ra, rb   | Compare equal             | VSEQ (v16 <= rt,ra,rb <= v29), mm=00|
 161 | SCMPLT16 rt, ra, rb   | Signed Compare less than        | !VSGT (v16 <= rt,ra,rb <= v23), mm=00|
 162 | SCMPLE16 rt, ra, rb   | Signed Compare less or equal    | VSLE (v16 <= rt,ra,rb <= v23), mm=00|
 163 | UCMPLT16 rt, ra, rb   | Unsigned Compare less than      | !VSGT (v24 <= rt,ra,rb <= v29), mm=00|
 164 | UCMPLE16 rt, ra, rb   | Unsigned Compare less or equal  | VSLE (v24 <= rt,ra,rb <= v29), mm=00|
 165
 166 ## 8-bit Comparison instructions
 167
 168 | Andes Mnemonic           | 8-bit Instruction        | Harmonised RVP Equivalent |
 169 | ------------------   | ------------------------- | ------------------- |
 170 | CMPEQ8 rt, ra, rb   | Compare equal             | VSEQ (v2 <= rt,ra,rb <= v7), mm=00|
 171 | SCMPLT8 rt, ra, rb   | Signed Compare less than        | !VSGT (v2 <= rt,ra,rb <= v7), mm=00|
 172 | SCMPLE8 rt, ra, rb   | Signed Compare less or equal    | VSLE (v2 <= rt,ra,rb <= v7), mm=00|
 173 | UCMPLT8 rt, ra, rb   | Unsigned Compare less than      | !VSGT (v8 <= rt,ra,rb <= v15), mm=00|
 174 | UCMPLE8 rt, ra, rb   | Unsigned Compare less or equal  | VSLE (v8 <= rt,ra,rb <= v15), mm=00|
 175
 176 ## 16-bit Miscellaneous instructions
 177
 178 | Andes Mnemonic      | 16-bit Instruction                | Harmonised RVP Equivalent |
 179 | ------------------  | ------------------------          | ------------------- |
 180 | SMIN16 rt, ra, rb   | Signed minimum                    | VMIN (v16 <= rt,ra,rb <= v23), mm=00|
 181 | UMIN16 rt, ra, rb   | Unsigned minimum                  | VMIN (v24 <= rt,ra,rb <= v29), mm=00|
 182 | SMAX16 rt, ra, rb   | Signed maximum                    | VMAX (v16 <= rt,ra,rb <= v23), mm=00|
 183 | UMAX16 rt, ra, rb   | Unsigned maximum                  | VMAX (v24 <= rt,ra,rb <= v29), mm=00|
 184 | SCLIP16 rt, ra, im  | Signed clip                       | ?VCLIP (v16 <= rt,ra,rb <= v23), mm=01|
 185 | UCLIP16 rt, ra, im  | Unsigned clip                     | ?VCLIP (v24 <= rt,ra,rb <= v29), mm=01|
 186 | KMUL16 rt, ra, rb   | Signed multiply 16x16->16         | VMUL (v16 <= rt,ra,rb <= v23), mm=01|
 187 | KMULX16 rt, ra, rb  | Signed crossed multiply 16x16->16 | |
 188 | SMUL16 rt, ra, rb   | Signed multiply 16x16->32         | VMUL (30 <= rt <= 31, v16 <= ra,rb <= v23), mm=00|
 189 | SMULX16 rt, ra, rb  | Signed crossed multiply 16x16->32 | |
 190 | UMUL16 rt, ra, rb   | Signed multiply 16x16->32         | VMUL (30 <= rt <= 31, v24 <= ra,rb <= r31), mm=00|
 191 | UMULX16 rt, ra, rb  | Signed crossed multiply 16x16->32 | |
 192 | KABS16 rt, ra       | Saturated absolute value          | VSGNX (v16 <= rt <= v29, v16 <= ra,rb <= v23, mm=01) |
 193
 194 ## 8-bit Miscellaneous instructions
 195
 196 | Andes Mnemonic           | 8-bit Instruction        | Harmonised RVP Equivalent |
 197 | ------------------   | ------------------------- | ------------------- |
 198 | SMIN8 rt, ra, rb   | Signed minimum           | VMIN (v2 <= rt,ra,rb <= v7), mm=00|
 199 | UMIN8 rt, ra, rb   | Unsigned minimum         | VMIN (v8 <= rt,ra,rb <= v15), mm=00|
 200 | SMAX8 rt, ra, rb   | Signed maximum           | VMAX (v2 <= rt,ra,rb <= v7), mm=00|
 201 | UMAX8 rt, ra, rb   | Unsigned maximum         | VMAX (v8 <= rt,ra,rb <= v15), mm=00|
 202 | KABS8 rt, ra       | Saturated absolute value | VSGNX (v2 <= rt <= v15, v2 <= ra,rb <= v8, mm=01) |
 203
 204 ## 8-bit Unpacking instructions
 205
 206 | Andes Mnemonic           | 8-bit Instruction       | Harmonised RVP Equivalent |
 207 | ------------------   | -------------------------   | ------------------- |
 208 | SUNPKD810 rt, ra     | Signed unpack bytes 1 & 0   | VMV (v16<= rt <= 23, v2 <= ra <= v7), mm=00|
 209 | SUNPKD820 rt, ra     | Signed unpack bytes 2 & 0   | |
 210 | SUNPKD830 rt, ra     | Signed unpack bytes 3 & 0   | |
 211 | SUNPKD831 rt, ra     | Signed unpack bytes 3 & 1   | |
 212 | ZUNPKD810 rt, ra     | Unsigned unpack bytes 1 & 0 | VMV (v24<= rt <= 31, v8 <= ra <= v15), mm=00|
 213 | ZUNPKD820 rt, ra     | Unsigned unpack bytes 2 & 0 | |
 214 | ZUNPKD830 rt, ra     | Unsigned unpack bytes 3 & 0 | |
 215 | ZUNPKD831 rt, ra     | Unsigned unpack bytes 3 & 1 | |