HDL_workflow/ECP5_FPGA.mdwn

   1 # ULX3S JTAG Connection with STLINKV2
   2
   3 Cross referenced with:
   4
   5 <https://bugs.libre-soc.org/show_bug.cgi?id=517>
   6
   7 <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-October/000873.html>
   8
   9 ## Original Instructions
  10
  11 See <https://bugs.libre-soc.org/show_bug.cgi?id=517#c0>
  12
  13 Checklist based on above
  14
  15 * For god's sake make sure you get this right, ***TRIPLE*** check everything.
  16
  17 * ***DO*** make sure to ***only*** drive an input as an input, and to ***only*** drive an output as an output.
  18
  19 * ***DO*** make sure to ***only*** wire up 5.0V to 5.0V and to ***only*** wire up GND to GND with the jumper-cables.
  20
  21 * ***DO*** make sure that ***before*** even ***thinking*** of uploading to and powering up the FPGA that everything has been ***THOROUGHLY*** triple-checked.
  22
  23 If you violate any of the above stated hard-and-fast rules you will end up learning the hard way by **DESTROYING** the FPGA.
  24
  25 | Done?   | Checklist Step |
  26 |---------|----------------|
  27 |         | Ensure there are **NO** wires connected to either the FPGA or the STLINKv2 |
  28 |         | Review the STLINKv2 Connector diagram and table |
  29 |         | Review the connections table for your model of fpga |
  30 |         | Ensure there are **ZERO** wires connected to either the FPGA or the STLINKv2, there should not even be a usb, mirco-usb, or power cable anywhere these components |
  31 |         | Make sure the orientation of your FPGA board and your STLINKv2 are the same as the images and diagrams on this page |
  32 |         | Wire each of the coloured jumper cables to the corresponding pins on the FPGA and the STLINKv2 according to the diagrams, tables, and images on this page |
  33
  34 Follow this section if you have the ULX3S FPGA:
  35
  36 | Done?   | Checklist Step |
  37 |---------|----------------|
  38 |         | Wire the **RED** jumper cable to (**ULX3S pin #2**) then wire it to (**STLINKv2 pin #2**), this will serve as the **Voltage Reference** signal (**VREF**) |
  39 |         | Wire the **BLACK** jumper cable to (**ULX3S pin #4**) then wire it to (**STLINKv2 pin #4**), this will serve as the **Ground** signal (**GND**) |
  40 |         | Wire the **GREEN** jumper cable to (**ULX3S pin #5**) then wire it to (**STLINKv2 pin #5**), this will serve as the **Test Data In** signal (**TDI**) |
  41 |         | Wire the **BLUE** jumper cable to (**ULX3S pin #6**) then wire it to (**STLINKv2 pin #7**), this will serve as the **Test Mode Select** signal (**TMS**) |
  42 |         | Wire the **WHITE** jumper cable to (**ULX3S pin #7**) then wire it to (**STLINKv2 pin #9**), this will serve as the **Test Clock** signal (**TCK**) |
  43 |         | Wire the **YELLOW** jumper cable to (**ULX3S pin #8**) then wire it to (**STLINKv2 pin #13**), this will serve as the **Test Data Out** signal (**TDO**) |
  44
  45 Follow this section if you have the Versa ECP5 FPGA:
  46
  47 | Done?   | Checklist Step |
  48 |---------|----------------|
  49 |         | Wire the **RED** jumper cable to (**X3 pin #39**) then wire it to (**STLINKv2 pin #2**), this will serve as the **Voltage Reference** signal (**VREF**) |
  50 |         | Wire the **BLACK** jumper cable to (**X3 pin #1**) then wire it to (**STLINKv2 pin #4**), this will serve as the **Ground** signal (**GND**) |
  51 |         | Wire the **GREEN** jumper cable to (**X3 pin #4**) then wire it to (**STLINKv2 pin #5**), this will serve as the **Test Data In** signal (**TDI**) |
  52 |         | Wire the **BLUE** jumper cable to (**X3 pin #5**) then wire it to (**STLINKv2 pin #7**), this will serve as the **Test Mode Select** signal (**TMS**) |
  53 |         | Wire the **WHITE** jumper cable to (**X3 pin #6**) then wire it to (**STLINKv2 pin #9**), this will serve as the **Test Clock** signal (**TCK**) |
  54 |         | Wire the **YELLOW** jumper cable to (**X3 pin #7**) then wire it to (**STLINKv2 pin #13**), this will serve as the **Test Data Out** signal (**TDO**) |
  55
  56 Final steps for both FPGA boards:
  57
  58 | Done?   | Checklist Step |
  59 |---------|----------------|
  60 |         | Check each jumper wire connection between the corresponding pins on the FPGA and the STLINKv2 **THREE** times |
  61 |         | I don't know what's next, need to review with lkcl |
  62
  63 ## Connecting the dots:
  64
  65 Accurate render of board for reference <https://github.com/emard/ulx3s/blob/master/pic/ulx3st.jpg>
  66
  67 STLINKV2 Pins and JTAG signals schematic/user guide <https://www.st.com/resource/en/user_manual/dm00026748-stlinkv2-incircuit-debuggerprogrammer-for-stm8-and-stm32-stmicroelectronics.pdf>
  68
  69 Litex platform file <https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/ulx3s.py>
  70
  71     ("gpio", 0,
  72         Subsignal"p", Pins("B11")),
  73         Subsignal("n", Pins("C11")),
  74         IOStandard("LVCMOS33")
  75     ),
  76     ("gpio", 1,
  77         Subsignal("p", Pins("A10")),
  78         Subsignal("n", Pins("A11")),
  79         IOStandard("LVCMOS33")
  80     ),
  81
  82 ULX3S FPGA constraints file <https://github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf#L341-342>
  83
  84     LOCATE COMP "gp[0]" SITE "B11"; # J1_5+  GP0 PCLK
  85     LOCATE COMP "gn[0]" SITE "C11"; # J1_5-  GN0 PCLK
  86     LOCATE COMP "gp[1]" SITE "A10"; # J1_7+  GP1 PCLK
  87     LOCATE COMP "gn[1]" SITE "A11"; # J1_7-  GN1 PCLK
  88
  89 ULX3S FPGA Schematic <https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf>
  90
  91 ```
  92 J1 J2 PIN number 1-40 is for FEMALE 90° ANGLED header.
  93 For MALE VERTICAL header, SWAP EVEN and ODD pin numbers.
  94
  95                     J1
  96
  97  Label  [GP{x}]|PCB pin label|[GN{x}] Label
  98            (Pin count +)(Pin count -)
  99 _________________V__________V________________
 100  IO VOLT REF 3V3 2  |3.3V|  1  NOT CONNECTED
 101            [GND] 4  | -| |  3  NOT CONNECTED
 102 PCLKT0_0   [GP0] 6  |  0 |  5  [GN0] PCLKC0_0
 103 PCLKT0_1   [GP1] 8  |  1 |  7  [GN1] PCLKC0_1
 104
 105
 106 GP,GN 0-7 single-ended connected to Bank0
 107 GP,GN 8-13 differential bidirectional connected to BANK7
 108 ```
 109
 110 Connecting all the dots:
 111
 112 ```
 113 Board pin # (count) | Board pin label # | FPGA IO PAD | GPIO # (n/p) |   Label  |
 114       5 (J1_5-)     |         0         |      C11    |    gn[0]     | PCLKC0_0 |
 115       6 (J1_5+)     |         0         |      B11    |    gp[0]     | PCLKT0_0 |
 116       7 (J1_7-)     |         1         |      A11    |    gn[1]     | PCLKC0_1 |
 117       8 (J1_7+)     |         1         |      A10    |    gp[1]     | PCLKT0_1 |
 118 ```
 119
 120 As noted in the schematic pins GP,GN 0-7 are single ended non-differential pairs, whereas pins GP,GN 8-13 I haven't mapped out here as they are bidirectional differential pairs.
 121
 122 Proposed FPGA External Pin to STLINK JTAG pin connections:
 123
 124 ```
 125    all pin #'s have headers pins on the fpga unless denoted as (no header)
 126  ______________________________________________________________________________
 127 |             | board |             |             |                |           |
 128 |             | label |             |             |STLINKV2  JTAG  |           |
 129 |    pin #    |   #   | FPGA IO PAD |GPIO # (n/p) | Pin #  (Signal)|Wire Colour|
 130 |_____________|_______|_____________|_____________|________________|___________|
 131 |1 (no header)|  3.3v |NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
 132 |2            |  3.3v | IO VOLT REF | IO VOLT REF |    2 (MCU VDD) |    Red    |
 133 |3 (no header)|-|(GND)|NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
 134 |4            |-|(GND)|    NONE     |     GND     |    4 (GND)     |   Black   |
 135 |5 (J1_5-)    |   0   |     C11     |    gn[0]    |    5 (JTDI)    |   Green   |
 136 |6 (J1_5+)    |   0   |     B11     |    gp[0]    |    7 (JTMS)    |   Blue    |
 137 |7 (J1_7-)    |   1   |     A11     |    gn[1]    |    9 (JTCK)    |   White   |
 138 |8 (J1_7+)    |   1   |     A10     |    gp[1]    |   13 (JTDO)    |   Yellow  |
 139 |_____________|_______|_____________|_____________|________________|___________|
 140 ```
 141
 142 Complete diagram:
 143
 144 ```
 145 Pins intentionally have no header or are not connected to the STLINKVT are marked
 146 and therefore have no value are marked with 'NOT'
 147
 148 (ST# JTAG) = (STLINKV2 pin #   JTAG signal name)
 149
 150
 151                              J1
 152             Wire                             Wire
 153            Colour [GP{x}]|PCB label|[GN{x}] Colour
 154 (ST# JTAG)        (Pin count +)(Pin count -)      (ST# JTAG)
 155  ________________________V__________V_________________________
 156 |                                                             |
 157 |( 2 JVDD) red    [VREF] 2  |3.3V|  1   NOT   NOT    NOT      |
 158 |( 4 JGND) black   [GND] 4  | -| |  3   NOT   NOT    NOT      |
 159 |( 7 JTMS) blue    [GP0] 6  |  0 |  5  [GN0] green (5 JTDI)   |
 160 |(13 JTDO) yellow  [GP1] 8  |  1 |  7  [GN1] white (9 JTCK)   |
 161 |_____________________________________________________________|
 162 ```
 163
 164 ## Images of wires on FPGA and on STLINKV2
 165
 166 Image of JTAG jumper wire connections on ULX3S FPGA side
 167
 168 [[!img HDL_workflow/jtag_wires_ulx3s_fpga.jpg size="200x" ]]
 169
 170 Image of JTAG jumper wire connections on STLINKV2 side
 171
 172 (same orientation as JTAG pinout documentation)
 173
 174 [[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2_same_orientation_as_jtag.jpg size="250x" ]]
 175
 176 Image of JTAG jumper wire connections on STLINKV2 side
 177
 178 (opposite orientation as JTAG pinout documentation,
 179
 180 same orientation as 'ST' text on STLINKV2 device)
 181
 182 [[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2_opposite_orientation_to_jtag.jpg size="x302" ]]
 183
 184 # STLinkV2 connector
 185
 186 [[!img 2020-11-03_14-08.png size="900x" ]]
 187
 188 [[!img 2020-11-03_14-09.png size="900x" ]]
 189
 190 # VERSA ECP5 Connections
 191
 192 Table of connections:
 193
 194 | X3  pin #   | FPGA IO PAD | STLinkv2       |Wire Colour|
 195 |-------------|-------------|----------------|-----------|
 196 |39 +3.3V     | 3.3V supply | 2 (MCU VDD)    |   Red     |
 197 |1 GND        | GND         | 4 (GND)        |   Black   |
 198 |4 IO29       |  B19        |    5 (TDI)     |   Green   |
 199 |5 IO30       |  B12        |    7 (TMS)     |   Blue    |
 200 |6 IO31       |  B9         |    9 (TCK)     |   White   |
 201 |7 IO32       |  E6         |   13 (TDO)     |   Yellow  |
 202
 203 [[!img 2020-11-03_13-22.png size="900x" ]]
 204
 205 [[!img 2020-11-03_13-25.png size="900x" ]]
 206
 207 [[!img versa_ecp5_x3_connector.jpg size="900x" ]]