HDL_workflow/ECP5_FPGA.mdwn

   1 # ULX3S JTAG Connection with STLINKV2
   2
   3 Cross referenced with:
   4
   5 <https://bugs.libre-soc.org/show_bug.cgi?id=517>
   6
   7 <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-October/000873.html>
   8
   9 ## Original Instructions
  10
  11 See <https://bugs.libre-soc.org/show_bug.cgi?id=517#c0>
  12
  13 TODO checklist based on above
  14
  15 | Done?   | FPGA IO PAD |
  16 |---------|-------------|
  17 |         | For god's sake do not get this wrong |
  18 |         | ***DO NOT*** drive an input as an output or vice-versa |
  19 |         | ***DO NOT*** wire up 5.0V to GND with the jumper-cables |
  20 |         | ***DO NOT*** randomly upload and power up the FPGA until this has been ***THOROUGHLY*** triple-checked |
  21 |         | If you violate any of the above stated hard-and-fast rules you will end up learning the hard way by **DESTROYING** the FPGA.
  22
  23 ## Connecting the dots:
  24
  25 Accurate render of board for reference <https://github.com/emard/ulx3s/blob/master/pic/ulx3st.jpg>
  26
  27 STLINKV2 Pins and JTAG signals schematic/user guide <https://www.st.com/resource/en/user_manual/dm00026748-stlinkv2-incircuit-debuggerprogrammer-for-stm8-and-stm32-stmicroelectronics.pdf>
  28
  29 Litex platform file <https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/ulx3s.py>
  30
  31     ("gpio", 0,
  32         Subsignal"p", Pins("B11")),
  33         Subsignal("n", Pins("C11")),
  34         IOStandard("LVCMOS33")
  35     ),
  36     ("gpio", 1,
  37         Subsignal("p", Pins("A10")),
  38         Subsignal("n", Pins("A11")),
  39         IOStandard("LVCMOS33")
  40     ),
  41
  42 ULX3S FPGA constraints file <https://github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf#L341-342>
  43
  44     LOCATE COMP "gp[0]" SITE "B11"; # J1_5+  GP0 PCLK
  45     LOCATE COMP "gn[0]" SITE "C11"; # J1_5-  GN0 PCLK
  46     LOCATE COMP "gp[1]" SITE "A10"; # J1_7+  GP1 PCLK
  47     LOCATE COMP "gn[1]" SITE "A11"; # J1_7-  GN1 PCLK
  48
  49 ULX3S FPGA Schematic <https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf>
  50
  51 ```
  52 J1 J2 PIN number 1-40 is for FEMALE 90° ANGLED header.
  53 For MALE VERTICAL header, SWAP EVEN and ODD pin numbers.
  54
  55                     J1
  56
  57  Label  [GP{x}]|PCB pin label|[GN{x}] Label
  58            (Pin count +)(Pin count -)
  59 _________________V__________V________________
  60  IO VOLT REF 3V3 2  |3.3V|  1  NOT CONNECTED
  61            [GND] 4  | -| |  3  NOT CONNECTED
  62 PCLKT0_0   [GP0] 6  |  0 |  5  [GN0] PCLKC0_0
  63 PCLKT0_1   [GP1] 8  |  1 |  7  [GN1] PCLKC0_1
  64
  65
  66 GP,GN 0-7 single-ended connected to Bank0
  67 GP,GN 8-13 differential bidirectional connected to BANK7
  68 ```
  69
  70 Connecting all the dots:
  71
  72 ```
  73 Board pin # (count) | Board pin label # | FPGA IO PAD | GPIO # (n/p) |   Label  |
  74       5 (J1_5-)     |         0         |      C11    |    gn[0]     | PCLKC0_0 |
  75       6 (J1_5+)     |         0         |      B11    |    gp[0]     | PCLKT0_0 |
  76       7 (J1_7-)     |         1         |      A11    |    gn[1]     | PCLKC0_1 |
  77       8 (J1_7+)     |         1         |      A10    |    gp[1]     | PCLKT0_1 |
  78 ```
  79
  80 As noted in the schematic pins GP,GN 0-7 are single ended non-differential pairs, whereas pins GP,GN 8-13 I haven't mapped out here as they are bidirectional differential pairs.
  81
  82 Proposed FPGA External Pin to STLINK JTAG pin connections:
  83
  84 ```
  85    all pin #'s have headers pins on the fpga unless denoted as (no header)
  86  ______________________________________________________________________________
  87 |             | board |             |             |                |           |
  88 |             | label |             |             |STLINKV2  JTAG  |           |
  89 |    pin #    |   #   | FPGA IO PAD |GPIO # (n/p) | Pin #  (Signal)|Wire Colour|
  90 |_____________|_______|_____________|_____________|________________|___________|
  91 |1 (no header)|  3.3v |NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
  92 |2            |  3.3v | IO VOLT REF | IO VOLT REF |    2 (MCU VDD) |    Red    |
  93 |3 (no header)|-|(GND)|NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
  94 |4            |-|(GND)|    NONE     |     GND     |    4 (GND)     |   Black   |
  95 |5 (J1_5-)    |   0   |     C11     |    gn[0]    |    5 (JTDI)    |   Green   |
  96 |6 (J1_5+)    |   0   |     B11     |    gp[0]    |    7 (JTMS)    |   Blue    |
  97 |7 (J1_7-)    |   1   |     A11     |    gn[1]    |    9 (JTCK)    |   White   |
  98 |8 (J1_7+)    |   1   |     A10     |    gp[1]    |   13 (JTDO)    |   Yellow  |
  99 |_____________|_______|_____________|_____________|________________|___________|
 100 ```
 101
 102 Complete diagram:
 103
 104 ```
 105 Pins intentionally have no header or are not connected to the STLINKVT are marked
 106 and therefore have no value are marked with 'NOT'
 107
 108 (ST# JTAG) = (STLINKV2 pin #   JTAG signal name)
 109
 110
 111                              J1
 112             Wire                             Wire
 113            Colour [GP{x}]|PCB label|[GN{x}] Colour
 114 (ST# JTAG)        (Pin count +)(Pin count -)      (ST# JTAG)
 115  ________________________V__________V_________________________
 116 |                                                             |
 117 |( 2 JVDD) red    [VREF] 2  |3.3V|  1   NOT   NOT    NOT      |
 118 |( 4 JGND) black   [GND] 4  | -| |  3   NOT   NOT    NOT      |
 119 |( 7 JTMS) blue    [GP0] 6  |  0 |  5  [GN0] green (5 JTDI)   |
 120 |(13 JTDO) yellow  [GP1] 8  |  1 |  7  [GN1] white (9 JTCK)   |
 121 |_____________________________________________________________|
 122 ```
 123
 124 ## Images of wires on FPGA and on STLINKV2
 125
 126 Image of JTAG jumper wire connections on ULX3S FPGA side
 127
 128 [[!img HDL_workflow/jtag_wires_ulx3s_fpga.jpg size="200x" ]]
 129
 130 Image of JTAG jumper wire connections on STLINKV2 side
 131
 132 (same orientation as JTAG pinout documentation)
 133
 134 [[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2_same_orientation_as_jtag.jpg size="250x" ]]
 135
 136 Image of JTAG jumper wire connections on STLINKV2 side
 137
 138 (opposite orientation as JTAG pinout documentation,
 139
 140 same orientation as 'ST' text on STLINKV2 device)
 141
 142 [[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2_opposite_orientation_to_jtag.jpg size="x302" ]]
 143
 144 # STLinkV2 connector
 145
 146 [[!img 2020-11-03_14-08.png size="900x" ]]
 147
 148 [[!img 2020-11-03_14-09.png size="900x" ]]
 149
 150 # VERSA ECP5 Connections
 151
 152 Table of connections:
 153
 154 | X3  pin #   | FPGA IO PAD | STLinkv2       |Wire Colour|
 155 |-------------|-------------|----------------|-----------|
 156 |1 GND        | GND         | 4 (GND)        |   Black   |
 157 |2 NC         | NC          |  NC            |    NC     |
 158 |39 +3.3V     | 3.3V supply | 2 (MCU VDD)    |   Red     |
 159 |4 IO29       |  B19        |    5 (TDI)     |   Green   |
 160 |5 IO30       |  B12        |    7 (TMS)     |   Blue    |
 161 |6 IO31       |  B9         |    9 (TCK)     |   White   |
 162 |7 IO32       |  E6         |   13 (TDO)     |   Yellow  |
 163
 164 [[!img 2020-11-03_13-22.png size="900x" ]]
 165
 166 [[!img 2020-11-03_13-25.png size="900x" ]]
 167
 168 [[!img versa_ecp5_x3_connector.jpg size="900x" ]]