1 # ULX3S JTAG Connection with STLINKV2
5 <https://bugs.libre-soc.org/show_bug.cgi?id=517>
7 <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-October/000873.html>
9 ## Original Instructions
11 See https://bugs.libre-soc.org/show_bug.cgi?id=517#c0
13 TODO checklist based on above
22 ## Connecting the dots:
24 Accurate render of board for reference <https://github.com/emard/ulx3s/blob/master/pic/ulx3st.jpg>
26 STLINKV2 Pins and JTAG signals schematic/user guide <https://www.st.com/resource/en/user_manual/dm00026748-stlinkv2-incircuit-debuggerprogrammer-for-stm8-and-stm32-stmicroelectronics.pdf>
28 Litex platform file <https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/ulx3s.py>
31 Subsignal"p", Pins("B11")),
32 Subsignal("n", Pins("C11")),
33 IOStandard("LVCMOS33")
36 Subsignal("p", Pins("A10")),
37 Subsignal("n", Pins("A11")),
38 IOStandard("LVCMOS33")
41 ULX3S FPGA constraints file <https://github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf#L341-342>
43 LOCATE COMP "gp[0]" SITE "B11"; # J1_5+ GP0 PCLK
44 LOCATE COMP "gn[0]" SITE "C11"; # J1_5- GN0 PCLK
45 LOCATE COMP "gp[1]" SITE "A10"; # J1_7+ GP1 PCLK
46 LOCATE COMP "gn[1]" SITE "A11"; # J1_7- GN1 PCLK
48 ULX3S FPGA Schematic <https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf>
51 J1 J2 PIN number 1-40 is for FEMALE 90° ANGLED header.
52 For MALE VERTICAL header, SWAP EVEN and ODD pin numbers.
56 Label [GP{x}]|PCB pin label|[GN{x}] Label
57 (Pin count +)(Pin count -)
58 _________________V__________V________________
59 IO VOLT REF 3V3 2 |3.3V| 1 NOT CONNECTED
60 [GND] 4 | -| | 3 NOT CONNECTED
61 PCLKT0_0 [GP0] 6 | 0 | 5 [GN0] PCLKC0_0
62 PCLKT0_1 [GP1] 8 | 1 | 7 [GN1] PCLKC0_1
65 GP,GN 0-7 single-ended connected to Bank0
66 GP,GN 8-13 differential bidirectional connected to BANK7
69 Connecting all the dots:
72 Board pin # (count) | Board pin label # | FPGA IO PAD | GPIO # (n/p) | Label |
73 5 (J1_5-) | 0 | C11 | gn[0] | PCLKC0_0 |
74 6 (J1_5+) | 0 | B11 | gp[0] | PCLKT0_0 |
75 7 (J1_7-) | 1 | A11 | gn[1] | PCLKC0_1 |
76 8 (J1_7+) | 1 | A10 | gp[1] | PCLKT0_1 |
79 As noted in the schematic pins GP,GN 0-7 are single ended non-differential pairs, whereas pins GP,GN 8-13 I haven't mapped out here as they are bidirectional differential pairs.
81 Proposed FPGA External Pin to STLINK JTAG pin connections:
84 all pin #'s have headers pins on the fpga unless denoted as (no header)
85 ______________________________________________________________________________
87 | | label | | |STLINKV2 JTAG | |
88 | pin # | # | FPGA IO PAD |GPIO # (n/p) | Pin # (Signal)|Wire Colour|
89 |_____________|_______|_____________|_____________|________________|___________|
90 |1 (no header)| 3.3v |NOT CONNECTED|NOT CONNECTED| NOT CONNECTED | NOT |
91 |2 | 3.3v | IO VOLT REF | IO VOLT REF | 2 (MCU VDD) | Red |
92 |3 (no header)|-|(GND)|NOT CONNECTED|NOT CONNECTED| NOT CONNECTED | NOT |
93 |4 |-|(GND)| NONE | GND | 4 (GND) | Black |
94 |5 (J1_5-) | 0 | C11 | gn[0] | 5 (JTDI) | Green |
95 |6 (J1_5+) | 0 | B11 | gp[0] | 7 (JTMS) | Blue |
96 |7 (J1_7-) | 1 | A11 | gn[1] | 9 (JTCK) | White |
97 |8 (J1_7+) | 1 | A10 | gp[1] | 13 (JTDO) | Yellow |
98 |_____________|_______|_____________|_____________|________________|___________|
104 Pins intentionally have no header or are not connected to the STLINKVT are marked
105 and therefore have no value are marked with 'NOT'
107 (ST# JTAG) = (STLINKV2 pin # JTAG signal name)
112 Colour [GP{x}]|PCB label|[GN{x}] Colour
113 (ST# JTAG) (Pin count +)(Pin count -) (ST# JTAG)
114 ________________________V__________V_________________________
116 |( 2 JVDD) red [VREF] 2 |3.3V| 1 NOT NOT NOT |
117 |( 4 JGND) black [GND] 4 | -| | 3 NOT NOT NOT |
118 |( 7 JTMS) blue [GP0] 6 | 0 | 5 [GN0] green (5 JTDI) |
119 |(13 JTDO) yellow [GP1] 8 | 1 | 7 [GN1] white (9 JTCK) |
120 |_____________________________________________________________|
123 ## Images of wires on FPGA and on STLINKV2
125 Image of JTAG jumper wire connections on ULX3S FPGA side
127 [[!img HDL_workflow/jtag_wires_ulx3s_fpga.jpg size="200x" ]]
129 Image of JTAG jumper wire connections on STLINKV2 side
131 (same orientation as JTAG pinout documentation)
133 [[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2_same_orientation_as_jtag.jpg size="250x" ]]
135 Image of JTAG jumper wire connections on STLINKV2 side
137 (opposite orientation as JTAG pinout documentation,
139 same orientation as 'ST' text on STLINKV2 device)
141 [[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2_opposite_orientation_to_jtag.jpg size="x302" ]]
145 [[!img 2020-11-03_14-08.png size="900x" ]]
147 [[!img 2020-11-03_14-09.png size="900x" ]]
149 # VERSA ECP5 Connections
151 Table of connections:
153 | X3 pin # | FPGA IO PAD | STLinkv2 |Wire Colour|
154 |-------------|-------------|----------------|-----------|
155 |1 GND | GND | 4 (GND) | Black |
156 |2 NC | NC | NC | NC |
157 |39 +3.3V | 3.3V supply | 2 (MCU VDD) | Red |
158 |4 IO29 | B19 | 5 (TDI) | Green |
159 |5 IO30 | B12 | 7 (TMS) | Blue |
160 |6 IO31 | B9 | 9 (TCK) | White |
161 |7 IO32 | E6 | 13 (TDO) | Yellow |
163 [[!img 2020-11-03_13-22.png size="900x" ]]
165 [[!img 2020-11-03_13-25.png size="900x" ]]
167 [[!img versa_ecp5_x3_connector.jpg size="900x" ]]