HDL_workflow/ECP5_FPGA.mdwn

   1 # ULX3S JTAG Connection with STLINKV2
   2
   3 Cross referenced with:
   4
   5 <https://bugs.libre-soc.org/show_bug.cgi?id=517>
   6
   7 <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-October/000873.html>
   8
   9 ## Original Instructions
  10
  11 See <https://bugs.libre-soc.org/show_bug.cgi?id=517#c0>
  12
  13 Checklist based on above
  14
  15 * For god's sake make sure you get this right, ***TRIPLE*** check everything.
  16
  17 * ***DO*** make sure to ***only*** drive an input as an input, and to ***only*** drive an output as an output.
  18
  19 * ***DO*** make sure to ***only*** wire up 5.0V to 5.0V and to ***only*** wire up GND to GND with the jumper-cables.
  20
  21 * ***DO*** make sure that ***before*** even ***thinking*** of uploading to and powering up the FPGA that everything has been ***THOROUGHLY*** triple-checked.
  22
  23 If you violate any of the above stated hard-and-fast rules you will end up learning the hard way by **DESTROYING** the FPGA.
  24
  25 To start we have to ensure we have a safe set up.
  26
  27 | Checklist Step |
  28 |----------------|
  29 | Ensure power is disconnected from FPGA |
  30 | Ensure STLINKV2 USB is disconnected |
  31 | Ensure FPGA USB is disconnected |
  32
  33 Now lets review all of the relevant material on this page before we begin the wiring process.
  34
  35 | Checklist Step |
  36 |----------------|
  37 | Review the STLINKv2 Connector diagram and table |
  38 | Review the connections table for your model of fpga |
  39 | Ensure the orientation of the FPGA and STLINKv2 match that of the images and diagrams on this page |
  40
  41 Next we will wire up the STLINKv2 and our FPGA in three separate stages.
  42
  43 * First attaching one end of a jumper cable to each necessary header pin on the STLINKv2.
  44
  45 * Then we will attach the end of a new jumper cable to each male header pin on the FPGA.
  46
  47 * Finally, we will connect the wires from the STLINKv2 to the wires from the FPGA by matching the colours of the wires.
  48
  49 This way you do not lose the connections when you want to disconnect and store the two devices. We are using FEMALE-TO-FEMALE jumper cables on the male header pins of each of the FPGA so that the wires do not randomly damage the bare PCB due to a short.
  50
  51 We will wire each of the pins on the the STLINKv2 according to the diagrams, tables, and images on this page.
  52
  53 | Action | Colour | Pin # | Pin Name |
  54 |--------|--------|-------|----------|
  55 | Attach | Red    |   2   |   VREF   |
  56 | Attach | Black  |   4   |   GND    |
  57 | Attach | Green  |   5   |   TDI    |
  58 | Attach | Blue   |   7   |   TMS    |
  59 | Attach | White  |   9   |   TCK    |
  60 | Attach | Yellow |  13   |   TDO    |
  61
  62 Next, we will wire each of the pins on the the FPGA according to the diagrams, tables, and images on this page.
  63
  64 Follow this section if you have the ULX3S FPGA:
  65
  66 | Action | Colour | Pin # | Pin Name |
  67 |--------|--------|-------|----------|
  68 | Attach | Red    |   2   |   VREF   |
  69 | Attach | Black  |   4   |   GND    |
  70 | Attach | Green  |   5   |   TDI    |
  71 | Attach | Blue   |   6   |   TMS    |
  72 | Attach | White  |   7   |   TCK    |
  73 | Attach | Yellow |   8   |   TDO    |
  74
  75 Follow this section if you have the Versa ECP5 FPGA:
  76
  77 | Action | Colour | X3 Pin # | Pin Name |
  78 |--------|--------|----------|----------|
  79 | Attach | Red    |    39    |   VREF   |
  80 | Attach | Black  |     1    |   GND    |
  81 | Attach | Green  |     4    |   TDI    |
  82 | Attach | Blue   |     5    |   TMS    |
  83 | Attach | White  |     6    |   TCK    |
  84 | Attach | Yellow |     7    |   TDO    |
  85
  86 Final steps for both FPGA boards:
  87
  88 | Checklist Step |
  89 |----------------|
  90 | Check each jumper wire connection between the corresponding pins on the FPGA and the STLINKv2 **THREE** times |
  91 | ***lckl*** check for ground loops? |
  92
  93
  94 Finally, we will connect the jumper cables of the same colour from STLINKv2 and the FPGA.
  95
  96 | Checklist Step |
  97 |----------------|
  98 | Attach the ends of the **RED** jumper cables   |
  99 | Attach the ends of the **BLACK** jumper cables |
 100 | Attach the ends of the **GREEN** jumper cables |
 101 | Attach the ends of the **BLUE** jumper cables  |
 102 | Attach the ends of the **WHITE** jumper cables |
 103 | Attach the ends of the **YELLO** jumper cables |
 104
 105 ## Connecting the dots:
 106
 107 Accurate render of board for reference <https://github.com/emard/ulx3s/blob/master/pic/ulx3st.jpg>
 108
 109 STLINKV2 Pins and JTAG signals schematic/user guide <https://www.st.com/resource/en/user_manual/dm00026748-stlinkv2-incircuit-debuggerprogrammer-for-stm8-and-stm32-stmicroelectronics.pdf>
 110
 111 Litex platform file <https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/ulx3s.py>
 112
 113     ("gpio", 0,
 114         Subsignal"p", Pins("B11")),
 115         Subsignal("n", Pins("C11")),
 116         IOStandard("LVCMOS33")
 117     ),
 118     ("gpio", 1,
 119         Subsignal("p", Pins("A10")),
 120         Subsignal("n", Pins("A11")),
 121         IOStandard("LVCMOS33")
 122     ),
 123
 124 ULX3S FPGA constraints file <https://github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf#L341-342>
 125
 126     LOCATE COMP "gp[0]" SITE "B11"; # J1_5+  GP0 PCLK
 127     LOCATE COMP "gn[0]" SITE "C11"; # J1_5-  GN0 PCLK
 128     LOCATE COMP "gp[1]" SITE "A10"; # J1_7+  GP1 PCLK
 129     LOCATE COMP "gn[1]" SITE "A11"; # J1_7-  GN1 PCLK
 130
 131 ULX3S FPGA Schematic <https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf>
 132
 133 ```
 134 J1 J2 PIN number 1-40 is for FEMALE 90° ANGLED header.
 135 For MALE VERTICAL header, SWAP EVEN and ODD pin numbers.
 136
 137                     J1
 138
 139  Label  [GP{x}]|PCB pin label|[GN{x}] Label
 140            (Pin count +)(Pin count -)
 141 _________________V__________V________________
 142  IO VOLT REF 3V3 2  |3.3V|  1  NOT CONNECTED
 143            [GND] 4  | -| |  3  NOT CONNECTED
 144 PCLKT0_0   [GP0] 6  |  0 |  5  [GN0] PCLKC0_0
 145 PCLKT0_1   [GP1] 8  |  1 |  7  [GN1] PCLKC0_1
 146
 147
 148 GP,GN 0-7 single-ended connected to Bank0
 149 GP,GN 8-13 differential bidirectional connected to BANK7
 150 ```
 151
 152 Connecting all the dots:
 153
 154 ```
 155 Board pin # (count) | Board pin label # | FPGA IO PAD | GPIO # (n/p) |   Label  |
 156       5 (J1_5-)     |         0         |      C11    |    gn[0]     | PCLKC0_0 |
 157       6 (J1_5+)     |         0         |      B11    |    gp[0]     | PCLKT0_0 |
 158       7 (J1_7-)     |         1         |      A11    |    gn[1]     | PCLKC0_1 |
 159       8 (J1_7+)     |         1         |      A10    |    gp[1]     | PCLKT0_1 |
 160 ```
 161
 162 As noted in the schematic pins GP,GN 0-7 are single ended non-differential pairs, whereas pins GP,GN 8-13 I haven't mapped out here as they are bidirectional differential pairs.
 163
 164 Proposed FPGA External Pin to STLINK JTAG pin connections:
 165
 166 ```
 167    all pin #'s have headers pins on the fpga unless denoted as (no header)
 168  ______________________________________________________________________________
 169 |             | board |             |             |                |           |
 170 |             | label |             |             |STLINKV2  JTAG  |           |
 171 |    pin #    |   #   | FPGA IO PAD |GPIO # (n/p) | Pin #  (Signal)|Wire Colour|
 172 |_____________|_______|_____________|_____________|________________|___________|
 173 |1 (no header)|  3.3v |NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
 174 |2            |  3.3v | IO VOLT REF | IO VOLT REF |    2 (MCU VDD) |    Red    |
 175 |3 (no header)|-|(GND)|NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
 176 |4            |-|(GND)|    NONE     |     GND     |    4 (GND)     |   Black   |
 177 |5 (J1_5-)    |   0   |     C11     |    gn[0]    |    5 (JTDI)    |   Green   |
 178 |6 (J1_5+)    |   0   |     B11     |    gp[0]    |    7 (JTMS)    |   Blue    |
 179 |7 (J1_7-)    |   1   |     A11     |    gn[1]    |    9 (JTCK)    |   White   |
 180 |8 (J1_7+)    |   1   |     A10     |    gp[1]    |   13 (JTDO)    |   Yellow  |
 181 |_____________|_______|_____________|_____________|________________|___________|
 182 ```
 183
 184 Complete diagram:
 185
 186 ```
 187 Pins intentionally have no header or are not connected to the STLINKVT are marked
 188 and therefore have no value are marked with 'NOT'
 189
 190 (ST# JTAG) = (STLINKV2 pin #   JTAG signal name)
 191
 192
 193                              J1
 194             Wire                             Wire
 195            Colour [GP{x}]|PCB label|[GN{x}] Colour
 196 (ST# JTAG)        (Pin count +)(Pin count -)      (ST# JTAG)
 197  ________________________V__________V_________________________
 198 |                                                             |
 199 |( 2 JVDD) red    [VREF] 2  |3.3V|  1   NOT   NOT    NOT      |
 200 |( 4 JGND) black   [GND] 4  | -| |  3   NOT   NOT    NOT      |
 201 |( 7 JTMS) blue    [GP0] 6  |  0 |  5  [GN0] green (5 JTDI)   |
 202 |(13 JTDO) yellow  [GP1] 8  |  1 |  7  [GN1] white (9 JTCK)   |
 203 |_____________________________________________________________|
 204 ```
 205
 206 ## Images of wires on FPGA and on STLINKV2
 207
 208 Image of JTAG jumper wire connections on ULX3S FPGA side
 209
 210 [[!img HDL_workflow/jtag_wires_ulx3s_fpga.jpg size="200x" ]]
 211
 212 Image of JTAG jumper wire connections on STLINKV2 side
 213
 214 (same orientation as JTAG pinout documentation)
 215
 216 [[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2_same_orientation_as_jtag.jpg size="250x" ]]
 217
 218 Image of JTAG jumper wire connections on STLINKV2 side
 219
 220 (opposite orientation as JTAG pinout documentation,
 221
 222 same orientation as 'ST' text on STLINKV2 device)
 223
 224 [[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2_opposite_orientation_to_jtag.jpg size="x302" ]]
 225
 226 # STLinkV2 connector
 227
 228 [[!img 2020-11-03_14-08.png size="900x" ]]
 229
 230 [[!img 2020-11-03_14-09.png size="900x" ]]
 231
 232 # VERSA ECP5 Connections
 233
 234 Table of connections:
 235
 236 | X3  pin #   | FPGA IO PAD | STLinkv2       |Wire Colour|
 237 |-------------|-------------|----------------|-----------|
 238 |39 +3.3V     | 3.3V supply | 2 (MCU VDD)    |   Red     |
 239 |1 GND        | GND         | 4 (GND)        |   Black   |
 240 |4 IO29       |  B19        |    5 (TDI)     |   Green   |
 241 |5 IO30       |  B12        |    7 (TMS)     |   Blue    |
 242 |6 IO31       |  B9         |    9 (TCK)     |   White   |
 243 |7 IO32       |  E6         |   13 (TDO)     |   Yellow  |
 244
 245 [[!img 2020-11-03_13-22.png size="900x" ]]
 246
 247 [[!img 2020-11-03_13-25.png size="900x" ]]
 248
 249 [[!img versa_ecp5_x3_connector.jpg size="900x" ]]