HDL_workflow/ECP5_FPGA.mdwn

   1 # ULX3S JTAG Connection with ft232r
   2
   3 Cross referenced with:
   4
   5 <https://bugs.libre-soc.org/show_bug.cgi?id=517>
   6
   7 <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-October/000873.html>
   8
   9 ## Original Instructions
  10
  11 See <https://bugs.libre-soc.org/show_bug.cgi?id=517#c0>
  12
  13 Checklist based on above
  14
  15 * For god's sake make sure you get this right, ***TRIPLE*** check everything.
  16
  17 * ***DO*** make sure to ***only*** drive an input as an input, and to ***only*** drive an output as an output.
  18
  19 * ***DO*** make sure to ***only*** wire up 3.3V to 3.3V and to ***only*** wire up GND to GND with the jumper-cables.
  20
  21 * ***DO*** make sure that ***before*** even ***thinking*** of uploading to and powering up the FPGA that everything has been ***THOROUGHLY*** triple-checked.
  22
  23 If you violate any of the above stated hard-and-fast rules you will end up learning the hard way by **DESTROYING** the FPGA.
  24
  25 To start we have to ensure we have a safe set up.
  26
  27 | Checklist Step |
  28 |----------------|
  29 | Ensure power is disconnected from FPGA |
  30 | Ensure ft232r USB is disconnected |
  31 | Ensure FPGA USB is disconnected |
  32
  33 Now lets review all of the relevant material on this page before we begin the wiring process.
  34
  35 | Checklist Step |
  36 |----------------|
  37 | Review the ft232r Connector diagram and table |
  38 | Review the connections table for your model of fpga |
  39 | Ensure the orientation of the FPGA and ft232r match that of the images and diagrams on this page |
  40
  41 Next we will wire up the ft232r and our FPGA in three separate stages.
  42
  43 * First we will attach one end of a ***MALE-TO-MALE (MTM)*** jumper cable to each necessary female header pin-hole on the ft232f.
  44
  45 * Then we will attach one end of a ***FEMALE-TO-FEMALE (FTF)*** cable to each male header pin on the FPGA.
  46
  47 * Finally, we will connect the wires from the ft232r to the wires from the FPGA by matching the colours of the wires.
  48
  49 This way you do not lose the connections when you want to disconnect and store the two devices. We are using FEMALE-TO-FEMALE jumper cables on the male header pins of the FPGA so that the wires do not randomly damage the bare PCB due to a short.
  50
  51 We will wire each of the pins on the the ft232r according to the diagrams, tables, and images on this page.
  52
  53 |   Action   | Colour | Pin Name |
  54 |------------|--------|----------|
  55 | Attach MTM | Black  |   GND    |
  56 | Attach MTM | Brown  |   TMS    |
  57 | Attach MTM | Red    |   VCC    |
  58 | Attach MTM | Orange |   TCK    |
  59 | Attach MTM | Yellow |   TDI    |
  60 | Attach MTM | Green  |   TDO    |
  61
  62 Next, we will wire each of the pins on the the FPGA according to the diagrams, tables, and images on this page.
  63
  64 Follow this section if you have the ULX3S FPGA:
  65
  66 |   Action   | Colour | Pin # | Pin Name |
  67 |------------|--------|-------|----------|
  68 | Attach FTF | Red    |   2   |   VREF   |
  69 | Attach FTF | Black  |   4   |   GND    |
  70 | Attach FTF | Yellow |   5   |   TDI    |
  71 | Attach FTF | Brown  |   6   |   TMS    |
  72 | Attach FTF | Orange |   7   |   TCK    |
  73 | Attach FTF | Green  |   8   |   TDO    |
  74
  75 Follow this section if you have the Versa ECP5 FPGA:
  76
  77 |   Action   | Colour | X3 Pin # | Pin Name |
  78 |------------|--------|----------|----------|
  79 | Attach FTF | Red    |    39    |   VREF   |
  80 | Attach FTF | Black  |     1    |   GND    |
  81 | Attach FTF | Yellow |     4    |   TDI    |
  82 | Attach FTF | Brown  |     5    |   TMS    |
  83 | Attach FTF | Orange |     6    |   TCK    |
  84 | Attach FTF | Green  |     7    |   TDO    |
  85
  86 Final steps for both FPGA boards:
  87
  88 | Checklist Step |
  89 |----------------|
  90 | Check each jumper wire connection between the corresponding pins on the FPGA and the ft232r **THREE** times |
  91 | ***lckl*** check for ground loops? |
  92
  93
  94 Finally, we will connect the jumper cables of the same colour from ft232r and the FPGA.
  95
  96 | Checklist Step |
  97 |----------------|
  98 | Attach the ends of the **RED** jumper cables    |
  99 | Attach the ends of the **BLACK** jumper cables  |
 100 | Attach the ends of the **YELLOW** jumper cables |
 101 | Attach the ends of the **BROWN** jumper cables  |
 102 | Attach the ends of the **ORANGE** jumper cables |
 103 | Attach the ends of the **GREEN** jumper cables  |
 104
 105 ***lckl if both the micro-usb cable and the ft232r GND and VCC wires are connected to the fpga will this result in volatage fighting where the fpga will be damaged?***
 106
 107 Finally, plug in the USB end of the USB-to-MicroUSB cable that is plugged into the ft232r into your computer. Begin testing the SOC on the FPGA (instructions to follow).
 108
 109 ## Connecting the dots:
 110
 111 Accurate render of board for reference <https://github.com/emard/ulx3s/blob/master/pic/ulx3st.jpg>
 112
 113 Litex platform file <https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/ulx3s.py>
 114
 115     ("gpio", 0,
 116         Subsignal"p", Pins("B11")),
 117         Subsignal("n", Pins("C11")),
 118         IOStandard("LVCMOS33")
 119     ),
 120     ("gpio", 1,
 121         Subsignal("p", Pins("A10")),
 122         Subsignal("n", Pins("A11")),
 123         IOStandard("LVCMOS33")
 124     ),
 125
 126 ULX3S FPGA constraints file <https://github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf#L341-342>
 127
 128     LOCATE COMP "gp[0]" SITE "B11"; # J1_5+  GP0 PCLK
 129     LOCATE COMP "gn[0]" SITE "C11"; # J1_5-  GN0 PCLK
 130     LOCATE COMP "gp[1]" SITE "A10"; # J1_7+  GP1 PCLK
 131     LOCATE COMP "gn[1]" SITE "A11"; # J1_7-  GN1 PCLK
 132
 133 ULX3S FPGA Schematic <https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf>
 134
 135 ```
 136 J1 J2 PIN number 1-40 is for FEMALE 90° ANGLED header.
 137 For MALE VERTICAL header, SWAP EVEN and ODD pin numbers.
 138
 139                     J1
 140
 141  Label  [GP{x}]|PCB pin label|[GN{x}] Label
 142            (Pin count +)(Pin count -)
 143 _________________V__________V________________
 144  IO VOLT REF 3V3 2  |3.3V|  1  NOT CONNECTED
 145            [GND] 4  | -| |  3  NOT CONNECTED
 146 PCLKT0_0   [GP0] 6  |  0 |  5  [GN0] PCLKC0_0
 147 PCLKT0_1   [GP1] 8  |  1 |  7  [GN1] PCLKC0_1
 148
 149
 150 GP,GN 0-7 single-ended connected to Bank0
 151 GP,GN 8-13 differential bidirectional connected to BANK7
 152 ```
 153
 154 Connecting all the dots:
 155
 156 ```
 157 Board pin # (count) | Board pin label # | FPGA IO PAD | GPIO # (n/p) |   Label  |
 158       5 (J1_5-)     |         0         |      C11    |    gn[0]     | PCLKC0_0 |
 159       6 (J1_5+)     |         0         |      B11    |    gp[0]     | PCLKT0_0 |
 160       7 (J1_7-)     |         1         |      A11    |    gn[1]     | PCLKC0_1 |
 161       8 (J1_7+)     |         1         |      A10    |    gp[1]     | PCLKT0_1 |
 162 ```
 163
 164 As noted in the schematic pins GP,GN 0-7 are single ended non-differential pairs, whereas pins GP,GN 8-13 I haven't mapped out here as they are bidirectional differential pairs.
 165
 166 ``` from http://openocd.org/doc/html/Debug-Adapter-Configuration.html#index-ftdi
 167 List of connections (default physical pin numbers for FT232R in 28-pin SSOP package):
 168
 169     - RXD(5) - TDI
 170     - TXD(1) - TCK
 171     - RTS(3) - TDO
 172     - CTS(11) - TMS
 173     - DTR(2) - TRST
 174     - DCD(10) - SRST
 175 ```
 176
 177 ``` from https://github.com/ntfreak/openocd/blob/master/src/jtag/drivers/ft232r.c#L79-L99
 178 /**
 179  * FT232R GPIO bit number to RS232 name
 180  */
 181 #define FT232R_BIT_COUNT 8
 182 static char *ft232r_bit_name_array[FT232R_BIT_COUNT] = {
 183         "TXD", /* 0: pin 1  TCK output */
 184         "RXD", /* 1: pin 5  TDI output */
 185         "RTS", /* 2: pin 3  TDO input */
 186         "CTS", /* 3: pin 11 TMS output */
 187         "DTR", /* 4: pin 2  /TRST output */
 188         "DSR", /* 5: pin 9  unused */
 189         "DCD", /* 6: pin 10 /SYSRST output */
 190         "RI"   /* 7: pin 6  unused */
 191 };
 192
 193 static int tck_gpio; /* initialized to 0 by default */
 194 static int tdi_gpio = 1;
 195 static int tdo_gpio = 2;
 196 static int tms_gpio = 3;
 197 static int ntrst_gpio = 4;
 198 static int nsysrst_gpio = 6;
 199 ```
 200
 201 ```from ft232 usb to 6 pin female header manual
 202  _________________________
 203 | Pin # | Name |  Colour  |
 204 |-------|------|----------|
 205 |   1   | GND  |  Black   |
 206 |   2   | CTS  |  Brown   |
 207 |   3   | VCC  |  Red     |
 208 |   4   | TXD  |  Orange  |
 209 |   5   | RXD  |  Yellow  |
 210 |   6   | RTS  |  Green   |
 211 |_______|______|__________|
 212 ```
 213
 214 ft232 pin and wire colour table converted to jtag signal names:
 215
 216 ```
 217  _________________________
 218 | Pin # | Name |  Colour  |
 219 |-------|------|----------|
 220 |   1   | GND  |  Black   |
 221 |   2   | TMS  |  Brown   |
 222 |   3   | VCC  |  Red     |
 223 |   4   | TCK  |  Orange  |
 224 |   5   | TDI  |  Yellow  |
 225 |   6   | TDO  |  Green   |
 226 |_______|______|__________|
 227 ```
 228
 229 Proposed FPGA External Pin to ft232r JTAG pin connections:
 230
 231 ```
 232    all pin #'s have headers pins on the fpga unless denoted as (no header)
 233  ______________________________________________________________________________
 234 |             | board |             |             |                |           |
 235 |             | label |             |             | ft232r   JTAG  |           |
 236 |    pin #    |   #   | FPGA IO PAD |GPIO # (n/p) | Pin #  (Signal)|Wire Colour|
 237 |_____________|_______|_____________|_____________|________________|___________|
 238 |1 (no header)|  3.3v |NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
 239 |2            |  3.3v | IO VOLT REF | IO VOLT REF |    3 (VCC)     |    Red    |
 240 |3 (no header)|-|(GND)|NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
 241 |4            |-|(GND)|    NONE     |     GND     |    1 (GND)     |   Black   |
 242 |5 (J1_5-)    |   0   |     C11     |    gn[0]    |    5 (TDI)     |   Yellow  |
 243 |6 (J1_5+)    |   0   |     B11     |    gp[0]    |    2 (TMS)     |   Brown   |
 244 |7 (J1_7-)    |   1   |     A11     |    gn[1]    |    4 (TCK)     |   Orange  |
 245 |8 (J1_7+)    |   1   |     A10     |    gp[1]    |    6 (TDO)     |   Green   |
 246 |_____________|_______|_____________|_____________|________________|___________|
 247 ```
 248
 249 Complete diagram:
 250
 251 ```
 252 Pins intentionally have no header or are not connected to the ft232 are marked
 253 and therefore have no value are marked with 'NOT'
 254
 255 (ft232r# JTAG) = (ft232r pin #   JTAG signal name)
 256
 257                              J1
 258             Wire                             Wire
 259            Colour [GP{x}]|PCB label|[GN{x}] Colour
 260 (ft232r# JTAG)   (Pin count +)(Pin count -)   (ft232r# JTAG)
 261  ______________________V__________V_______________________
 262 |                                                         |
 263 |(3 VCC) red    [VREF] 2  |3.3V|  1   NOT   NOT    NOT    |
 264 |(1 GND) black   [GND] 4  | -| |  3   NOT   NOT    NOT    |
 265 |(2 TMS) brown   [GP0] 6  |  0 |  5  [GN0] yellow (5 TDI) |
 266 |(6 TDO) green   [GP1] 8  |  1 |  7  [GN1] orange (4 TCK) |
 267 |_________________________________________________________|
 268 ```
 269
 270 ## Images of wires on ulx3s FPGA and on ft232r (lkcl to update images for Versa ECP5)
 271
 272 Image of JTAG jumper wire connections on ULX3S FPGA side:
 273
 274 [[!img HDL_workflow/ulx3s_fpga_jtag_wires.jpg size="500x" ]]
 275
 276 Image of JTAG jumper wire connections on ft232r side:
 277
 278 [[!img HDL_workflow/ft232r_jtag_wires.jpg size="500x" ]]
 279
 280 Colour markings on ft232r side:
 281
 282 [[!img HDL_workflow/ft232.png size="500x" ]]
 283
 284 # VERSA ECP5 Connections
 285
 286 Table of connections:
 287
 288 | X3  pin #   | FPGA IO PAD |  ft232r   |Wire Colour|
 289 |-------------|-------------|-----------|-----------|
 290 |   39 +3.3V  | 3.3V supply |  3 (VCC)  |   Red     |
 291 |    1 GND    |     GND     |  1 (GND)  |   Black   |
 292 |    4 IO29   |     B19     |  5 (TDI)  |   Yellow  |
 293 |    5 IO30   |     B12     |  2 (TMS)  |   Brown   |
 294 |    6 IO31   |     B9      |  4 (TCK)  |   Orange  |
 295 |    7 IO32   |     E6      |  6 (TDO)  |   Green   |