HDL_workflow/ECP5_FPGA.mdwn

   1 # ULX3S JTAG Connection with STLINKV2
   2
   3 Cross referenced with:
   4
   5 <https://bugs.libre-soc.org/show_bug.cgi?id=517>
   6
   7 <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-October/000873.html>
   8
   9 ## Original Instructions
  10
  11 lkcl:
  12
  13
  14 > the JTAG TAP interface on the *FPGA* is hard-coded silicon.
  15
  16 > the JTAG TAP interface connected on the processor and soft-implemented
  17 > *by* the FPGA is likely completely inaccessible until someone
  18 > allocates pins to "jtag_tdi/tdo/tms/tck" in the litex config.
  19 >
  20 > which means: someone's going to have to to through this file:
  21 > <https://github.com/enjoy-digital/litex/blob/master/litex/boards/platforms/ulx3s.py#L72>
  22 > (which defines the pin allocations)
  23 >
  24 > and in this file do some Voodoo Magic on this file's TestSoC:
  25 > <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/litex/florent/ulx3s85f.py;hb=HEAD>
  26 >
  27 > similar to these four lines:
  28 > <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/litex/florent/ls180soc.py;h=4279effcffe2fbf15f877e9b2a1b76beab248dac;hb=HEAD#l460>
  29 >
  30 > but instead doing something like... err....
  31 >
  32 >    gpio0_pads = platform.reqiest("gpio", 0) # because back in ulx3s.py there's gpio 0, 1, and 2
  33 >
  34 >    self.comb += self.cpu.jtag_tck.eq(gpio0_pads.p) # because again back in that file there are 2 pins, one named "p", one named "n"
  35 >
  36 >    self.comb += self.cpu.jtag_tms.eq(gpio0_pads.n) # etc.
  37 >
  38 > and then request gpio1 for the other 2 pins
  39 >
  40 > theeeen you'll need to go back to that ulx3s.py litex platform file,
  41 > look up the pin names B11, C11, A10, A11, and find out what the hell
  42 > they are, whether they're suitable for use.
  43 >
  44 > if they are, then great! these are what you wire up the STLINKv2 to,
  45 > according to what you decided to connect to just above.
  46 >
  47 > but for god's sake do not get this wrong, such as driving an input as
  48 > an output or vice-versa, or wiring up 5.0V to GND with those
  49 > jumper-cables.
  50 >
  51 > do *NOT* randomly upload and power up the ulx3s until this has been
  52 > THOROUGHLY triple-checked. or, you are entirely free to not bother
  53 > and to end up learning the hard way by destroying the FPGA.
  54
  55 ## Connecting the dots:
  56
  57 Accurate render of board for reference <https://github.com/emard/ulx3s/blob/master/pic/ulx3st.jpg>
  58
  59 STLINKV2 Pins and JTAG signals schematic/user guide <https://www.st.com/resource/en/user_manual/dm00026748-stlinkv2-incircuit-debuggerprogrammer-for-stm8-and-stm32-stmicroelectronics.pdf>
  60
  61 Litex platform file <https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/ulx3s.py>
  62
  63     ("gpio", 0,
  64         Subsignal"p", Pins("B11")),
  65         Subsignal("n", Pins("C11")),
  66         IOStandard("LVCMOS33")
  67     ),
  68     ("gpio", 1,
  69         Subsignal("p", Pins("A10")),
  70         Subsignal("n", Pins("A11")),
  71         IOStandard("LVCMOS33")
  72     ),
  73
  74 ULX3S FPGA constraints file <https://github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf#L341-342>
  75
  76     LOCATE COMP "gp[0]" SITE "B11"; # J1_5+  GP0 PCLK
  77     LOCATE COMP "gn[0]" SITE "C11"; # J1_5-  GN0 PCLK
  78     LOCATE COMP "gp[1]" SITE "A10"; # J1_7+  GP1 PCLK
  79     LOCATE COMP "gn[1]" SITE "A11"; # J1_7-  GN1 PCLK
  80
  81 ULX3S FPGA Schematic <https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf>
  82
  83 ```
  84 J1 J2 PIN number 1-40 is for FEMALE 90° ANGLED header.
  85 For MALE VERTICAL header, SWAP EVEN and ODD pin numbers.
  86
  87                     J1
  88
  89  Label  [GP{x}]|PCB pin label|[GN{x}] Label
  90            (Pin count +)(Pin count -)
  91 _________________V__________V________________
  92  IO VOLT REF 3V3 2  |3.3V|  1  NOT CONNECTED
  93            [GND] 4  | -| |  3  NOT CONNECTED
  94 PCLKT0_0   [GP0] 6  |  0 |  5  [GN0] PCLKC0_0
  95 PCLKT0_1   [GP1] 8  |  1 |  7  [GN1] PCLKC0_1
  96
  97
  98 GP,GN 0-7 single-ended connected to Bank0
  99 GP,GN 8-13 differential bidirectional connected to BANK7
 100 ```
 101
 102 Connecting all the dots:
 103
 104 ```
 105 Board pin # (count) | Board pin label # | FPGA IO PAD | GPIO # (n/p) |   Label  |
 106       5 (J1_5-)     |         0         |      C11    |    gn[0]     | PCLKC0_0 |
 107       6 (J1_5+)     |         0         |      B11    |    gp[0]     | PCLKT0_0 |
 108       7 (J1_7-)     |         1         |      A11    |    gn[1]     | PCLKC0_1 |
 109       8 (J1_7+)     |         1         |      A10    |    gp[1]     | PCLKT0_1 |
 110 ```
 111
 112 As noted in the schematic pins GP,GN 0-7 are single ended non-differential pairs, whereas pins GP,GN 8-13 I haven't mapped out here as they are bidirectional differential pairs.
 113
 114 Proposed FPGA External Pin to STLINK JTAG pin connections:
 115
 116 ```
 117    all pin #'s have headers pins on the fpga unless denoted as (no header)
 118  ______________________________________________________________________________
 119 |             | board |             |             |                |           |
 120 |             | label |             |             |STLINKV2  JTAG  |           |
 121 |    pin #    |   #   | FPGA IO PAD |GPIO # (n/p) | Pin #  (Signal)|Wire Colour|
 122 |_____________|_______|_____________|_____________|________________|___________|
 123 |1 (no header)|  3.3v |NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
 124 |2            |  3.3v | IO VOLT REF | IO VOLT REF |    2 (MCU VDD) |    Red    |
 125 |3 (no header)|-|(GND)|NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
 126 |4            |-|(GND)|    NONE     |     GND     |    4 (GND)     |   Black   |
 127 |5 (J1_5-)    |   0   |     C11     |    gn[0]    |    5 (JTDI)    |   Green   |
 128 |6 (J1_5+)    |   0   |     B11     |    gp[0]    |    7 (JTMS)    |   Blue    |
 129 |7 (J1_7-)    |   1   |     A11     |    gn[1]    |    9 (JTCK)    |   White   |
 130 |8 (J1_7+)    |   1   |     A10     |    gp[1]    |   13 (JTDO)    |   Yellow  |
 131 |_____________|_______|_____________|_____________|________________|___________|
 132 ```
 133
 134 Complete diagram:
 135
 136 ```
 137 Pins intentionally have no header or are not connected to the STLINKVT are marked
 138 and therefore have no value are marked with 'NOT'
 139
 140 (ST# JTAG) = (STLINKV2 pin #   JTAG signal name)
 141
 142
 143                              J1
 144             Wire                             Wire
 145            Colour [GP{x}]|PCB label|[GN{x}] Colour
 146 (ST# JTAG)        (Pin count +)(Pin count -)      (ST# JTAG)
 147  ________________________V__________V_________________________
 148 |                                                             |
 149 |( 2 JVDD) red    [VREF] 2  |3.3V|  1   NOT   NOT    NOT      |
 150 |( 4 JGND) black   [GND] 4  | -| |  3   NOT   NOT    NOT      |
 151 |( 7 JTMS) blue    [GP0] 6  |  0 |  5  [GN0] green (5 JTDI)   |
 152 |(13 JTDO) yellow  [GP1] 8  |  1 |  7  [GN1] white (9 JTCK)   |
 153 |_____________________________________________________________|
 154 ```
 155
 156 ## Images of wires on FPGA and on STLINKV2
 157
 158 [[!img HDL_workflow/jtag_wires_ulx3s_fpga.jpg size="200x" ]] [[!img HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg size="200x" ]]
 159
 160 ## Questions
 161
 162 Luke do the labels of PCLK[C|T]0_[0|1] and GR_PCLK0_[0|1] have any significance? Should we be using the CLK labeled pins specifically for JTAG or specifically avoid using them for JTAG?
 163
 164 Additionally, does the note in the schematic about needing to swap EVEN and ODD pin numbers if using MALE VERTICAL header instead of FEMALE 90° ANGLED header apply to us?
 165
 166 # STLinkV2 connector
 167
 168 [[!img 2020-11-03_14-08.png size="900x" ]]
 169
 170 [[!img 2020-11-03_14-09.png size="900x" ]]
 171
 172 # VERSA ECP5 Connections
 173
 174 Table of connections:
 175
 176 | X3  pin #   | FPGA IO PAD | STLinkv2       |Wire Colour|
 177 |-------------|-------------|----------------|-----------|
 178 |1 GND        | GND         | 4 (GND)        |   Black   |
 179 |2 NC         | NC          |  NC            |    NC     |
 180 |3 +2V5       | 2.5V supply | 2 (MCU VDD)    |   Red     |
 181 |4 IO29       |  B19        |    5 (TDI)     |   Green   |
 182 |5 IO30       |  B12        |    7 (TMS)     |   Blue    |
 183 |6 IO31       |  B9         |    9 (TCK)     |   White   |
 184 |7 IO32       |  E6         |   13 (TDO)     |   Yellow  |
 185
 186 [[!img 2020-11-03_13-22.png size="900x" ]]
 187
 188 [[!img 2020-11-03_13-25.png size="900x" ]]
 189
 190 [[!img versa_ecp5_x3_connector.jpg size="900x" ]]