HDL_workflow/ECP5_FPGA.mdwn

   1 # ULX3S JTAG Connection with ft232r
   2
   3 Cross referenced with:
   4
   5 <https://bugs.libre-soc.org/show_bug.cgi?id=517>
   6
   7 <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-October/000873.html>
   8
   9 ## Original Instructions
  10
  11 See <https://bugs.libre-soc.org/show_bug.cgi?id=517#c0>
  12
  13 Checklist based on above
  14
  15 * For god's sake make sure you get this right, ***TRIPLE*** check everything.
  16
  17 * ***DO*** make sure to ***only*** drive an input as an input, and to ***only*** drive an output as an output.
  18
  19 * ***DO*** make sure to ***only*** wire up 3.3V to 3.3V and to ***only*** wire up GND to GND with the jumper-cables.
  20
  21 * ***DO*** make sure that ***before*** even ***thinking*** of uploading to and powering up the FPGA that everything has been ***THOROUGHLY*** triple-checked.
  22
  23 If you violate any of the above stated hard-and-fast rules you will end up learning the hard way by **DESTROYING** the FPGA.
  24
  25 To start we have to ensure we have a safe set up.
  26
  27 | Checklist Step |
  28 |----------------|
  29 | Ensure power is disconnected from FPGA |
  30 | Ensure ft232r USB is disconnected |
  31 | Ensure FPGA USB is disconnected |
  32
  33 Now lets review all of the relevant material on this page before we begin the wiring process.
  34
  35 | Checklist Step |
  36 |----------------|
  37 | Review the ft232r Connector diagram and table |
  38 | Review the connections table for your model of fpga |
  39 | Ensure the orientation of the FPGA and ft232r match that of the images and diagrams on this page |
  40
  41 Next we will wire up the ft232r and our FPGA in three separate stages.
  42
  43 * First we will attach one end of a ***MALE-TO-MALE (MTM)*** jumper cable to each necessary female header pin-hole on the ft232f.
  44
  45 * Then we will attach one end of a ***FEMALE-TO-FEMALE (FTF)*** cable to each male header pin on the FPGA.
  46
  47 * Finally, we will connect the wires from the ft232r to the wires from the FPGA by matching the colours of the wires.
  48
  49 This way you do not lose the connections when you want to disconnect and store the two devices. We are using FEMALE-TO-FEMALE jumper cables on the male header pins of the FPGA so that the wires do not randomly damage the bare PCB due to a short.
  50
  51 We will wire each of the pins on the the ft232r according to the diagrams, tables, and images on this page.
  52
  53 According to [https://www.sparkfun.com/datasheets/IC/FT232R_v104.pdf], page 8 - Table 1: pin 4 - VCCIO - should be supplied *by the FPGA*.
  54
  55 According to Jacob: you nearly always need gnd for a return path for the current. if you don't have a return path right near the signal lines, it will totally mess up high speed signals, due to the extra inductance caused by the loop through the signal and off to a ground somewhere.
  56
  57 Therefore we will not attach any jumpers to the red VCC wire of the ft232r cable, nor the fpga.
  58
  59 |   Action   | Colour | Pin Name |
  60 |------------|--------|----------|
  61 | Attach MTM | Black  |   GND    |
  62 | Attach MTM | Brown  |   TMS    |
  63 | Attach MTM | Orange |   TCK    |
  64 | Attach MTM | Yellow |   TDI    |
  65 | Attach MTM | Green  |   TDO    |
  66
  67 Next, we will wire each of the pins on the the FPGA according to the diagrams, tables, and images on this page.
  68
  69 Follow this section if you have the ULX3S FPGA:
  70
  71 |   Action   | Colour | Pin # | Pin Name |
  72 |------------|--------|-------|----------|
  73 | Attach FTF | Black  |   4   |   GND    |
  74 | Attach FTF | Yellow |   5   |   TDI    |
  75 | Attach FTF | Brown  |   6   |   TMS    |
  76 | Attach FTF | Orange |   7   |   TCK    |
  77 | Attach FTF | Green  |   8   |   TDO    |
  78
  79 Follow this section if you have the Versa ECP5 FPGA:
  80
  81 |   Action   | Colour | X3 Pin # | Pin Name |
  82 |------------|--------|----------|----------|
  83 | Attach FTF | Black  |     1    |   GND    |
  84 | Attach FTF | Yellow |     4    |   TDI    |
  85 | Attach FTF | Brown  |     5    |   TMS    |
  86 | Attach FTF | Orange |     6    |   TCK    |
  87 | Attach FTF | Green  |     7    |   TDO    |
  88
  89 Final steps for both FPGA boards:
  90
  91 | Checklist Step |
  92 |----------------|
  93 | Check each jumper wire connection between the corresponding pins on the FPGA and the ft232r **THREE** times |
  94
  95 Finally, we will connect the jumper cables of the same colour from ft232r and the FPGA.
  96
  97 | Checklist Step |
  98 |----------------|
  99 | Attach the ends of the **BLACK** jumper cables  |
 100 | Attach the ends of the **YELLOW** jumper cables |
 101 | Attach the ends of the **BROWN** jumper cables  |
 102 | Attach the ends of the **ORANGE** jumper cables |
 103 | Attach the ends of the **GREEN** jumper cables  |
 104
 105 Finally, plug in the USB end of the USB-to-MicroUSB cable that is plugged into the ft232r into your computer. Begin testing the SOC on the FPGA (instructions to follow).
 106
 107 ## Connecting the dots:
 108
 109 Accurate render of board for reference <https://github.com/emard/ulx3s/blob/master/pic/ulx3st.jpg>
 110
 111 Litex platform file <https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/ulx3s.py>
 112
 113     ("gpio", 0,
 114         Subsignal"p", Pins("B11")),
 115         Subsignal("n", Pins("C11")),
 116         IOStandard("LVCMOS33")
 117     ),
 118     ("gpio", 1,
 119         Subsignal("p", Pins("A10")),
 120         Subsignal("n", Pins("A11")),
 121         IOStandard("LVCMOS33")
 122     ),
 123
 124 ULX3S FPGA constraints file <https://github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf#L341-342>
 125
 126     LOCATE COMP "gp[0]" SITE "B11"; # J1_5+  GP0 PCLK
 127     LOCATE COMP "gn[0]" SITE "C11"; # J1_5-  GN0 PCLK
 128     LOCATE COMP "gp[1]" SITE "A10"; # J1_7+  GP1 PCLK
 129     LOCATE COMP "gn[1]" SITE "A11"; # J1_7-  GN1 PCLK
 130
 131 ULX3S FPGA Schematic <https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf>
 132
 133 ```
 134 J1 J2 PIN number 1-40 is for FEMALE 90° ANGLED header.
 135 For MALE VERTICAL header, SWAP EVEN and ODD pin numbers.
 136
 137                     J1
 138
 139  Label     [GP{x}]|PCB pin label|[GN{x}] Label
 140              (Pin count +)(Pin count -)
 141 ___________________V__________V________________
 142 NOT CONNECTED 3V3  2  |3.3V|  1  NOT CONNECTED
 143              [GND] 4  | -| |  3  NOT CONNECTED
 144 PCLKT0_0     [GP0] 6  |  0 |  5  [GN0] PCLKC0_0
 145 PCLKT0_1     [GP1] 8  |  1 |  7  [GN1] PCLKC0_1
 146
 147
 148 GP,GN 0-7 single-ended connected to Bank0
 149 GP,GN 8-13 differential bidirectional connected to BANK7
 150 ```
 151
 152 Connecting all the dots:
 153
 154 ```
 155 Board pin # (count) | Board pin label # | FPGA IO PAD | GPIO # (n/p) |   Label  |
 156       5 (J1_5-)     |         0         |      C11    |    gn[0]     | PCLKC0_0 |
 157       6 (J1_5+)     |         0         |      B11    |    gp[0]     | PCLKT0_0 |
 158       7 (J1_7-)     |         1         |      A11    |    gn[1]     | PCLKC0_1 |
 159       8 (J1_7+)     |         1         |      A10    |    gp[1]     | PCLKT0_1 |
 160 ```
 161
 162 As noted in the schematic pins GP,GN 0-7 are single ended non-differential pairs, whereas pins GP,GN 8-13 I haven't mapped out here as they are bidirectional differential pairs.
 163
 164 ft232 pin and wire colour table converted to jtag signal names:
 165
 166 ```
 167  _________________________
 168 | Pin # | Name |  Colour  |
 169 |-------|------|----------|
 170 |   1   | GND  |  Black   |
 171 |   2   | TMS  |  Brown   |
 172 |   4   | TCK  |  Orange  |
 173 |   5   | TDI  |  Yellow  |
 174 |   6   | TDO  |  Green   |
 175 |_______|______|__________|
 176 ```
 177
 178 Proposed FPGA External Pin to ft232r JTAG pin connections:
 179
 180 ```
 181    all pin #'s have headers pins on the fpga unless denoted as (no header)
 182  ______________________________________________________________________________
 183 |             | board |             |             |                |           |
 184 |             | label |             |             | ft232r   JTAG  |           |
 185 |    pin #    |   #   | FPGA IO PAD |GPIO # (n/p) | Pin #  (Signal)|Wire Colour|
 186 |_____________|_______|_____________|_____________|________________|___________|
 187 |1 (no header)|  3.3v |NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
 188 |2            |  3.3v | IO VOLT REF | IO VOLT REF | NOT CONNECTED  |    NOT    |
 189 |3 (no header)|-|(GND)|NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
 190 |4            |-|(GND)|    NONE     |     GND     |    1 (GND)     |   Black   |
 191 |5 (J1_5-)    |   0   |     C11     |    gn[0]    |    5 (TDI)     |   Yellow  |
 192 |6 (J1_5+)    |   0   |     B11     |    gp[0]    |    2 (TMS)     |   Brown   |
 193 |7 (J1_7-)    |   1   |     A11     |    gn[1]    |    4 (TCK)     |   Orange  |
 194 |8 (J1_7+)    |   1   |     A10     |    gp[1]    |    6 (TDO)     |   Green   |
 195 |_____________|_______|_____________|_____________|________________|___________|
 196 ```
 197
 198 Complete diagram:
 199
 200 ```
 201 Pins intentionally have no header or are not connected to the ft232 are marked
 202 and therefore have no value are marked with 'NOT'
 203
 204 (ft232r# JTAG) = (ft232r pin #   JTAG signal name)
 205
 206                              J1
 207             Wire                             Wire
 208            Colour [GP{x}]|PCB label|[GN{x}] Colour
 209 (ft232r# JTAG)   (Pin count +)(Pin count -)   (ft232r# JTAG)
 210  ______________________V__________V_______________________
 211 |                                                         |
 212 |NOT      NOT   [VREF] 2  |3.3V|  1   NOT   NOT     NOT   |
 213 |(1 GND) black   [GND] 4  | -| |  3   NOT   NOT     NOT   |
 214 |(2 TMS) brown   [GP0] 6  |  0 |  5  [GN0] yellow (5 TDI) |
 215 |(6 TDO) green   [GP1] 8  |  1 |  7  [GN1] orange (4 TCK) |
 216 |_________________________________________________________|
 217 ```
 218
 219 ## Images of wires on FPGA and on ft232r
 220
 221 Image of JTAG jumper wire connections on ULX3S FPGA side
 222
 223 [[!img HDL_workflow/ulx3s_fpga_jtag_wires.jpg size="500x" ]]
 224
 225 Image of JTAG jumper wire connections on ft232r side
 226
 227 [[!img HDL_workflow/ft232r_jtag_wires.jpg size="500x" ]]
 228
 229 # VERSA ECP5 Connections
 230
 231 Table of connections:
 232
 233 | X3  pin #   | FPGA IO PAD |  ft232r   |Wire Colour|
 234 |-------------|-------------|-----------|-----------|
 235 |    1 GND    |     GND     |  1 (GND)  |   Black   |
 236 |    4 IO29   |     B19     |  5 (TDI)  |   Yellow  |
 237 |    5 IO30   |     B12     |  2 (TMS)  |   Brown   |
 238 |    6 IO31   |     B9      |  4 (TCK)  |   Orange  |
 239 |    7 IO32   |     E6      |  6 (TDO)  |   Green   |
 240
 241 [[!img 2020-11-03_13-22.png size="900x" ]]
 242
 243 [[!img 2020-11-03_13-25.png size="900x" ]]
 244
 245 [[!img versa_ecp5_x3_connector.jpg size="900x" ]]