HDL_workflow/ECP5_FPGA.mdwn

   1 # ULX3S JTAG Connection with ft232r
   2
   3 Note: this page is for connecting a *secondary* JTAG connection to
   4 the Libre-SOC Core, in order to test the actual HDL implementation
   5 of JTAG.  "Normal" JTAG documentation instructs you how to connect
   6 to the **FPGA** hard-macro JTAG port (in some fashion).  Whilst the
   7 FPGA has a JTAG port as a hard-macro these instructions do **not**
   8 apply to that: they apply **specifically** to actual implementation
   9 in HDL of a JTAG TAP interface suitable for deployment on an ASIC,
  10 and, consequently, in order to test that, four GPIO pads had to be
  11 picked to bring those signals out.  These instructions describe how
  12 to correctly wire up an FT232r to connect to those four GPIO pads.
  13
  14 Cross referenced with:
  15
  16 <https://bugs.libre-soc.org/show_bug.cgi?id=517>
  17
  18 <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-October/000873.html>
  19
  20 <https://www.amazon.co.uk/DSD-TECH-adapter-FT232RL-Compatible/dp/B07BBPX8B8/ref=sr_1_11?dchild=1&keywords=ft232&qid=1632498288&s=amazon-devices&sr=1-11>
  21
  22 <https://www.amazon.co.uk/Elegoo-120pcs-Multicolored-Breadboard-arduino-colorful/dp/B01EV70C78/>
  23
  24 ## Original Instructions
  25
  26 See <https://bugs.libre-soc.org/show_bug.cgi?id=517#c0>
  27
  28 Checklist based on above
  29
  30 * For god's sake make sure you get this right, ***TRIPLE*** check everything.
  31
  32 * ***DO*** make sure to ***only*** drive an input as an input, and to ***only*** drive an output as an output.
  33
  34 * ***DO*** make sure to ***only*** wire up 3.3V to 3.3V and to ***only*** wire up GND to GND with the jumper-cables.
  35
  36 * ***DO*** make sure that ***before*** even ***thinking*** of uploading to and powering up the FPGA that everything has been ***THOROUGHLY*** triple-checked.
  37
  38 If you violate any of the above stated hard-and-fast rules you will end up learning the hard way by **DESTROYING** the FPGA.
  39
  40 To start we have to ensure we have a safe set up.
  41
  42 | Checklist Step |
  43 |----------------|
  44 | Ensure power is disconnected from FPGA |
  45 | Ensure ft232r USB is disconnected |
  46 | Ensure FPGA USB is disconnected |
  47
  48 Now lets review all of the relevant material on this page before we begin the wiring process.
  49
  50 | Checklist Step |
  51 |----------------|
  52 | Review the ft232r Connector diagram and table |
  53 | Review the connections table for your model of fpga |
  54 | Ensure the orientation of the FPGA and ft232r match that of the images and diagrams on this page |
  55
  56 Next we will wire up the ft232r and our FPGA in three separate stages.
  57
  58 * First we will attach one end of a ***MALE-TO-MALE (MTM)*** jumper cable to each necessary female header pin-hole on the ft232f.
  59
  60 * Then we will attach one end of a ***FEMALE-TO-FEMALE (FTF)*** cable to each male header pin on the FPGA.
  61
  62 * Finally, we will connect the wires from the ft232r to the wires from the FPGA by matching the colours of the wires.
  63
  64 This way you do not lose the connections when you want to disconnect and store the two devices. We are using FEMALE-TO-FEMALE jumper cables on the male header pins of the FPGA so that the wires do not randomly damage the bare PCB due to a short.
  65
  66 We will wire each of the pins on the the ft232r according to the diagrams, tables, and images on this page.
  67
  68 |   Action   | Colour | Pin Name |
  69 |------------|--------|----------|
  70 | Attach MTM | Black  |   GND    |
  71 | Attach MTM | Brown  |   TMS    |
  72 | Attach MTM | Red    |   VCC    |
  73 | Attach MTM | Orange |   TCK    |
  74 | Attach MTM | Yellow |   TDI    |
  75 | Attach MTM | Green  |   TDO    |
  76
  77 Next, we will wire each of the pins on the the FPGA according to the diagrams, tables, and images on this page.
  78
  79 Follow this section if you have the ULX3S FPGA:
  80
  81 |   Action   | Colour | Pin # | Pin Name |
  82 |------------|--------|-------|----------|
  83 | Attach FTF | Red    |   2   |   VREF   |
  84 | Attach FTF | Black  |   4   |   GND    |
  85 | Attach FTF | Yellow |   5   |   TDI    |
  86 | Attach FTF | Brown  |   6   |   TMS    |
  87 | Attach FTF | Orange |   7   |   TCK    |
  88 | Attach FTF | Green  |   8   |   TDO    |
  89
  90 Follow this section if you have the Versa ECP5 FPGA:
  91
  92 |   Action   | Colour | X3 Pin # | Pin Name |
  93 |------------|--------|----------|----------|
  94 | Attach FTF | Red    |    39    |   VREF   |
  95 | Attach FTF | Black  |     1    |   GND    |
  96 | Attach FTF | Yellow |     4    |   TDI    |
  97 | Attach FTF | Brown  |     5    |   TMS    |
  98 | Attach FTF | Orange |     6    |   TCK    |
  99 | Attach FTF | Green  |     7    |   TDO    |
 100
 101 Final steps for both FPGA boards:
 102
 103 | Checklist Step |
 104 |----------------|
 105 | Check each jumper wire connection between the corresponding pins on the FPGA and the ft232r **THREE** times |
 106 | ***lckl*** check for ground loops? |
 107
 108
 109 Finally, we will connect the jumper cables of the same colour from ft232r and the FPGA.
 110
 111 | Checklist Step |
 112 |----------------|
 113 | Attach the ends of the **RED** jumper cables    |
 114 | Attach the ends of the **BLACK** jumper cables  |
 115 | Attach the ends of the **YELLOW** jumper cables |
 116 | Attach the ends of the **BROWN** jumper cables  |
 117 | Attach the ends of the **ORANGE** jumper cables |
 118 | Attach the ends of the **GREEN** jumper cables  |
 119
 120 ***lckl if both the micro-usb cable and the ft232r GND and VCC wires are connected to the fpga will this result in volatage fighting where the fpga will be damaged?***
 121
 122 Finally, plug in the USB end of the USB-to-MicroUSB cable that is plugged into the ft232r into your computer. Begin testing the SOC on the FPGA (instructions to follow).
 123
 124 ## Connecting the dots:
 125
 126 Accurate render of board for reference <https://github.com/emard/ulx3s/blob/master/pic/ulx3st.jpg>
 127
 128 Litex platform file <https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/ulx3s.py>
 129
 130     ("gpio", 0,
 131         Subsignal"p", Pins("B11")),
 132         Subsignal("n", Pins("C11")),
 133         IOStandard("LVCMOS33")
 134     ),
 135     ("gpio", 1,
 136         Subsignal("p", Pins("A10")),
 137         Subsignal("n", Pins("A11")),
 138         IOStandard("LVCMOS33")
 139     ),
 140
 141 ULX3S FPGA constraints file <https://github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf#L341-342>
 142
 143     LOCATE COMP "gp[0]" SITE "B11"; # J1_5+  GP0 PCLK
 144     LOCATE COMP "gn[0]" SITE "C11"; # J1_5-  GN0 PCLK
 145     LOCATE COMP "gp[1]" SITE "A10"; # J1_7+  GP1 PCLK
 146     LOCATE COMP "gn[1]" SITE "A11"; # J1_7-  GN1 PCLK
 147
 148 ULX3S FPGA Schematic <https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf>
 149
 150 ```
 151 J1 J2 PIN number 1-40 is for FEMALE 90° ANGLED header.
 152 For MALE VERTICAL header, SWAP EVEN and ODD pin numbers.
 153
 154                     J1
 155
 156  Label  [GP{x}]|PCB pin label|[GN{x}] Label
 157            (Pin count +)(Pin count -)
 158 _________________V__________V________________
 159  IO VOLT REF 3V3 2  |3.3V|  1  NOT CONNECTED
 160            [GND] 4  | -| |  3  NOT CONNECTED
 161 PCLKT0_0   [GP0] 6  |  0 |  5  [GN0] PCLKC0_0
 162 PCLKT0_1   [GP1] 8  |  1 |  7  [GN1] PCLKC0_1
 163
 164
 165 GP,GN 0-7 single-ended connected to Bank0
 166 GP,GN 8-13 differential bidirectional connected to BANK7
 167 ```
 168
 169 Connecting all the dots:
 170
 171 ```
 172 Board pin # (count) | Board pin label # | FPGA IO PAD | GPIO # (n/p) |   Label  |
 173       5 (J1_5-)     |         0         |      C11    |    gn[0]     | PCLKC0_0 |
 174       6 (J1_5+)     |         0         |      B11    |    gp[0]     | PCLKT0_0 |
 175       7 (J1_7-)     |         1         |      A11    |    gn[1]     | PCLKC0_1 |
 176       8 (J1_7+)     |         1         |      A10    |    gp[1]     | PCLKT0_1 |
 177 ```
 178
 179 As noted in the schematic pins GP,GN 0-7 are single ended non-differential pairs, whereas pins GP,GN 8-13 I haven't mapped out here as they are bidirectional differential pairs.
 180
 181 ``` from http://openocd.org/doc/html/Debug-Adapter-Configuration.html#index-ftdi
 182 List of connections (default physical pin numbers for FT232R in 28-pin SSOP package):
 183
 184     - RXD(5) - TDI
 185     - TXD(1) - TCK
 186     - RTS(3) - TDO
 187     - CTS(11) - TMS
 188     - DTR(2) - TRST
 189     - DCD(10) - SRST
 190 ```
 191
 192 ``` from https://github.com/ntfreak/openocd/blob/master/src/jtag/drivers/ft232r.c#L79-L99
 193 /**
 194  * FT232R GPIO bit number to RS232 name
 195  */
 196 #define FT232R_BIT_COUNT 8
 197 static char *ft232r_bit_name_array[FT232R_BIT_COUNT] = {
 198         "TXD", /* 0: pin 1  TCK output */
 199         "RXD", /* 1: pin 5  TDI output */
 200         "RTS", /* 2: pin 3  TDO input */
 201         "CTS", /* 3: pin 11 TMS output */
 202         "DTR", /* 4: pin 2  /TRST output */
 203         "DSR", /* 5: pin 9  unused */
 204         "DCD", /* 6: pin 10 /SYSRST output */
 205         "RI"   /* 7: pin 6  unused */
 206 };
 207
 208 static int tck_gpio; /* initialized to 0 by default */
 209 static int tdi_gpio = 1;
 210 static int tdo_gpio = 2;
 211 static int tms_gpio = 3;
 212 static int ntrst_gpio = 4;
 213 static int nsysrst_gpio = 6;
 214 ```
 215
 216 ```from ft232 usb to 6 pin female header manual
 217
 218 ft232 pin and wire colour table converted to jtag signal names:
 219
 220 ```
 221 |-------|------|--------|----------|
 222 | Pin # | JTAG |  FT232 | Colour   |
 223 |-------|------|--------|----------|
 224 |   1   | VCC  | VCC    |  Red     |
 225 |   2   | GND  | GND    |  Black   |
 226 |   3   | TCK  | TXD    |  White   |
 227 |   4   | TDI  | RXD    |  Green   |
 228 |   5   | TDO  | RTS    |  Yellow  |
 229 |   6   | TMS  | CTS    |  Blue    |
 230 |-------|------|--------|----------|
 231 ```
 232 Proposed FPGA External Pin to ft232r JTAG pin connections:
 233
 234 ```
 235    all pin #'s have headers pins on the fpga unless denoted as (no header)
 236  ______________________________________________________________________________
 237 |             | board |             |             |                |           |
 238 |             | label |             |             | ft232r   JTAG  |           |
 239 |    pin #    |   #   | FPGA IO PAD |GPIO # (n/p) | Pin #  (Signal)|Wire Colour|
 240 |_____________|_______|_____________|_____________|________________|___________|
 241 |1 (no header)|  3.3v |NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
 242 |2            |  3.3v | IO VOLT REF | IO VOLT REF |    3 (VCC)     |    Red    |
 243 |3 (no header)|-|(GND)|NOT CONNECTED|NOT CONNECTED| NOT CONNECTED  |    NOT    |
 244 |4            |-|(GND)|    NONE     |     GND     |    1 (GND)     |   Black   |
 245 |5 (J1_5-)    |   0   |     C11     |    gn[0]    |    5 (TDI)     |   Green   |
 246 |6 (J1_5+)    |   0   |     B11     |    gp[0]    |    2 (TMS)     |   Blue    |
 247 |7 (J1_7-)    |   1   |     A11     |    gn[1]    |    4 (TCK)     |   White   |
 248 |8 (J1_7+)    |   1   |     A10     |    gp[1]    |    6 (TDO)     |   Yellow  |
 249 |_____________|_______|_____________|_____________|________________|___________|
 250 ```
 251
 252 Complete diagram:
 253
 254 ```
 255 Pins intentionally have no header or are not connected to the ft232 are marked
 256 and therefore have no value are marked with 'NOT'
 257
 258 (ft232r# JTAG) = (ft232r pin #   JTAG signal name)
 259
 260                              J1
 261             Wire                             Wire
 262            Colour [GP{x}]|PCB label|[GN{x}] Colour
 263 (ft232r# JTAG)   (Pin count +)(Pin count -)   (ft232r# JTAG)
 264  ______________________V__________V_______________________
 265 |                                                         |
 266 |(3 VCC) red    [VREF] 2  |3.3V|  1   NOT   NOT    NOT    |
 267 |(1 GND) black   [GND] 4  | -| |  3   NOT   NOT    NOT    |
 268 |(2 TMS) Blue    [GP0] 6  |  0 |  5  [GN0] Green  (5 TDI) |
 269 |(6 TDO) Yellow  [GP1] 8  |  1 |  7  [GN1] White  (4 TCK) |
 270 |_________________________________________________________|
 271 ```
 272
 273 ## Images of wires on ulx3s FPGA and on ft232r (lkcl to update images for Versa ECP5)
 274
 275 Image of JTAG jumper wire connections on ULX3S FPGA side:
 276
 277 [[!img HDL_workflow/ulx3s_fpga_jtag_wires.jpg size="500x" ]]
 278
 279 Image of JTAG jumper wire connections on ft232r side:
 280
 281 [[!img HDL_workflow/ft232r_jtag_wires.jpg size="500x" ]]
 282
 283 Colour markings on ft232r side:
 284
 285 [[!img HDL_workflow/ft232.png size="500x" ]]
 286
 287 # VERSA ECP5 Connections
 288
 289 Table of connections:
 290
 291 | X3  pin #   | FPGA IO PAD |  Function | FT232  | Wire Colour|
 292 |-------------|-------------|-----------|--------|------------|
 293 |   39 +3.3V  | 3.3V supply |    (VCC)  | VREF   |   Red      |
 294 |    1 GND    |     GND     |    (GND)  | GND    |   Black    |
 295 |    4 IO29   |     B19     |    (TDI)  | RXD    |   Green    |
 296 |    5 IO30   |     B12     |    (TMS)  | CTS    |   Blue     |
 297 |    6 IO31   |     B9      |    (TCK)  | TXD    |   White    |
 298 |    7 IO32   |     E6      |    (TDO)  | RTS    |   Yellow   |
 299
 300 [[!img 2020-11-03_13-22.png size="900x" ]]
 301
 302 [[!img 2020-11-03_13-25.png size="900x" ]]
 303
 304 [[!img versa_ecp5_x3_connector.jpg size="900x" ]]
 305