add cesar
[libreriscv.git] / HDL_workflow / HyperRAM.mdwn
1 # HyperRAM connections
2
3 * jumper wires <https://www.amazon.co.uk/Elegoo-120pcs-Multicolored-Breadboard-arduino-colorful/dp/B01EV70C78/>
4 * Note that cables have to be really short, they may need to
5 be constructed and soldered
6 <https://www.amazon.co.uk/HALJIA-2-54mm-Dupont-Jumper-Connectors/dp/B06WWB66WL/>
7 * nmigen [hyperram.py](https://git.libre-soc.org/?p=lambdasoc.git;a=blob;f=lambdasoc/periph/hyperram.py;hb=HEAD) module
8 * Winbond Datasheet for Quad 1bitsqared PMOD:
9 <https://ftp.libre-soc.org/W956x8MBYA_64Mb_HyperBus_pSRAM_TFBGA24_datasheet_A01-005_20211208.pdf>
10 * Winbond Verilog Model for W956A8MBY:
11 <https://www.winbond.com/resource-files/W956x8MBY_verilog_p.zip>
12 * [[shakti/m_class/HyperRAM]]
13 * <https://github.com/icebreaker-fpga/icebreaker-pmod/tree/master/quadhyperram>
14 * <https://hackaday.io/project/168594-feather-wing-pmod-adapter> <https://github.com/TomKeddie/prj-pmod-feather>
15
16 ```
17 from nmigen.resources.memory import HyperRAMResources
18 hyperram_ios = HyperRAMResources(cs_n="B13 C13 A12 A13",
19 dq="E14 C11 B10 E12 D12 A9 D11 D14",
20 rwds="C14", rst_n="E13", clk_p="D13",
21 clk_n="A14", # only in DDR mode
22 attrs=IOStandard("LVCMOS33"))
23 self.platform.add_extension(hyperram_ios)
24 io = self.platform.request("hyperram")
25 hyperram = HyperRAM(io=io, phy_kls=HyperRAMPHY,
26 latency=7) # Winbond W956D8MBYA
27 # latency=6 for Cypress S27KL0641DABHI020
28 ```
29
30 ## 1bitsquared HyperRAM PMOD
31
32 * <https://1bitsquared.de/products/pmod-hyperram>
33
34 | Pin | Function | Colour | Pin | Function | Colour |
35 | --- | -------- | ---------| --- | -------- | ---------|
36 | Top 7 | CS3N | Blue | Top 1 | CS2N | Green |
37 | Top 8 | CS1N | Purple | Top 2 | CS0N | Orange |
38 | Top 9 | RESETN | Grey | Top 3 | CK | Yellow |
39 | Top 10 | RWDS | White | Top 4 | CKN | Brown |
40 | Top 11 | GND | Black | Top 5 | GND | Black |
41 | Top 12 | 3V3 | Red | Top 6 | 3V3 | Red |
42
43 | Pin | Function | Colour | Pin | Function | Colour |
44 | --- | -------- | ---------| --- | -------- | ---------|
45 | Bot 7 | DQ7 | Blue | Bot 1 | DQ0 | Green |
46 | Bot 8 | DQ6 | Purple | Bot 2 | DQ1 | Orange |
47 | Bot 9 | DQ5 | Grey | Bot 3 | DQ2 | Yellow |
48 | Bot 10 | DQ4 | White | Bot 4 | DQ3 | Brown |
49 | Bot 11 | GND | Black | Bot 5 | GND | Black |
50 | Bot 12 | 3V3 | Red | Bot 6 | 3V3 | Red |
51
52 [[!img HDL_workflow/ENtvxc9WwAAGyzl.png size="400x" ]]
53 [[!img HDL_workflow/ENxOeloWsAMSw5u.jpeg size="500x" ]]
54
55 [[!img HDL_workflow/ENw4bZ8W4AM8FOS.png size="900x" ]]
56
57 [[!img HDL_workflow/pmod-hyperram-64mbit-dual-pmod_large.jpg size="700x" ]]
58
59 [[!img HDL_workflow/hyperram_connected_pmod.jpg size="700x" ]]
60
61 # VERSA ECP5 Connections
62
63 Table of connections:
64
65 | X4 pin # | FPGA IO PAD | Function | Wire Colour|
66 |-------------|-------------|-----------|------------|
67 | 3 IO0 | A12 | (CS2N) | Green |
68 | 4 IO1 | A13 | (CS3N) | Blue |
69 | 5 IO2 | B13 | (CS0N) | Orange |
70 | 6 IO3 | C13 | (CS1N) | Purple |
71 | 7 IO4 | D13 | (CK) | Yellow |
72 | 8 IO5 | E13 | (RSTN) | Grey |
73 | 9 IO6 | A14 | (CKN) | Brown |
74 | 10 IO7 | C14 | (RWDS) | White |
75 | 11 IO8 | D14 | (DQ7) | Blue |
76 | 12 IO9 | E14 | (DQ0) | Green |
77 | 13 IO10 | D11 | (DQ6) | Purple |
78 | 14 IO11 | C11 | (DQ1) | Orange |
79 | 15 IO12 | A9 | (DQ5) | Grey |
80 | 16 IO13 | B10 | (DQ2) | Yellow |
81 | 17 IO14 | D12 | (DQ4) | White |
82 | 18 IO15 | E12 | (DQ3) | Brown |
83 | 19 GND | GND | (GND) | Black |
84 | 20 +3.3V | 3.3V supply | (VCC) | Red |
85
86 [[!img HDL_workflow/versa_ecp5_x4_hyperram.png size="900x" ]]
87
88 [[!img 2020-11-03_13-25.png size="900x" ]]
89
90 # Digilent Arty a7-100t Connections
91
92 See <https://digilent.com/reference/_media/reference/programmable-logic/arty/arty_rm.pdf>
93
94 [[!img 2022-03-22_15-56.png size="900x" ]]