676eff7ed8f3c307979da6466b051e8b29af8806
[riscv-isa-sim.git] / README
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2 RISC-V ISA Simulator
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4 # Author : Andrew Waterman
5 # Date : June 19, 2011
6 # Version : (under version control)
7
8 The RISC-V ISA Simulator implements a functional model of one or more
9 RISC-V processors.
10
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12 Build Steps
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14
15 % mkdir build
16 % cd build
17 % ../configure
18 % make
19 % [sudo] make install
20
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22 Usage
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24
25 The riscv-isa-run program is not usually invoked directly; rather, fesvr, the
26 Front-End Server, invokes riscv-isa-run. fesvr and riscv-pk must be installed
27 to simulate a RISC-V user program using riscv-isa-run.
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30 Compiling and Running a Simple C Program
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32
33 Install riscv-isa-run (see Build Steps), then install the following additional
34 packages: riscv-fesvr, riscv-gcc, riscv-pk.
35
36 Write a short C program and name it hello.c. Then, compile it into a RISC-V
37 ELF binary named hello:
38
39 % riscv-gcc -o hello hello.c
40
41 Now you can simulate the program:
42
43 % riscv-fesvr hello
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46 Simulating a New Instruction
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48
49 Adding an instruction to the simulator requires two steps:
50
51 1. Describe the instruction's functional behavior in the file
52 riscv/insns/<new_instruction_name>.h. Examine other instructions
53 in that directory as a starting point.
54
55 2. Add the instruction to the riscv-opcodes package:
56
57 % cd ../riscv-opcodes
58 % vi opcodes // add a line for the new instruction
59 % make install
60
61 3. Rebuild the simulator.