TLB/src/ariane/ptw.py

   1 """
   2 # Copyright 2018 ETH Zurich and University of Bologna.
   3 # Copyright and related rights are licensed under the Solderpad Hardware
   4 # License, Version 0.51 (the "License"); you may not use this file except in
   5 # compliance with the License.  You may obtain a copy of the License at
   6 # http:#solderpad.org/licenses/SHL-0.51. Unless required by applicable law
   7 # or agreed to in writing, software, hardware and materials distributed under
   8 # this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
   9 # CONDITIONS OF ANY KIND, either express or implied. See the License for the
  10 # specific language governing permissions and limitations under the License.
  11 #
  12 # Author: David Schaffenrath, TU Graz
  13 # Author: Florian Zaruba, ETH Zurich
  14 # Date: 24.4.2017
  15 # Description: Hardware-PTW
  16
  17 /* verilator lint_off WIDTH */
  18 import ariane_pkg::*;
  19 """
  20
  21 from nmigen import Const, Signal, Cat, Module
  22 from nmigen.hdl.ast import ArrayProxy
  23 from nmigen.cli import verilog, rtlil
  24 from math import log2
  25
  26 DCACHE_SET_ASSOC = 8
  27 CONFIG_L1D_SIZE =  32*1024
  28 DCACHE_INDEX_WIDTH = int(log2(CONFIG_L1D_SIZE / DCACHE_SET_ASSOC))
  29 DCACHE_TAG_WIDTH = 56 - DCACHE_INDEX_WIDTH
  30
  31
  32 class DCacheReqI:
  33     def __init__(self):
  34         self.address_index = Signal(DCACHE_INDEX_WIDTH)
  35         self.address_tag = Signal(DCACHE_TAG_WIDTH)
  36         self.data_wdata = Signal(64)
  37         self.data_req = Signal()
  38         self.data_we = Signal()
  39         self.data_be = Signal(8)
  40         self.data_size = Signal(2)
  41         self.kill_req = Signal()
  42         self.tag_valid = Signal()
  43
  44     def ports(self):
  45         return [self.address_index, self.address_tag,
  46                 self.data_wdata, self.data_req,
  47                 self.data_we, self.data_be, self.data_size,
  48                 self.kill_req, self.tag_valid,
  49             ]
  50
  51 class DCacheReqO:
  52     def __init__(self):
  53         self.data_gnt = Signal()
  54         self.data_rvalid = Signal()
  55         self.data_rdata = Signal(64)
  56
  57     def ports(self):
  58         return [ self.data_gnt, self.data_rvalid, self.data_rdata]
  59
  60
  61 ASID_WIDTH = 8
  62
  63 class PTE: #(RecordObject):
  64     def __init__(self):
  65         self.reserved = Signal(10)
  66         self.ppn = Signal(44)
  67         self.rsw = Signal(2)
  68         self.d = Signal()
  69         self.a = Signal()
  70         self.g = Signal()
  71         self.u = Signal()
  72         self.x = Signal()
  73         self.w = Signal()
  74         self.r = Signal()
  75         self.v = Signal()
  76
  77     def flatten(self):
  78         return Cat(*self.ports())
  79
  80     def eq(self, x):
  81         if isinstance(x, ArrayProxy):
  82             res = []
  83             for o in self.ports():
  84                 i = getattr(x, o.name)
  85                 res.append(i)
  86             x = Cat(*res)
  87         else:
  88             x = x.flatten()
  89         return self.flatten().eq(x)
  90
  91     def ports(self):
  92         return [self.reserved, self.ppn, self.rsw, self.d, self.a, self.g,
  93                 self.u, self.x, self.w, self.r, self.v]
  94
  95
  96 class TLBUpdate:
  97     def __init__(self):
  98         self.valid = Signal()      # valid flag
  99         self.is_2M = Signal()
 100         self.is_1G = Signal()
 101         self.vpn = Signal(27)
 102         self.asid = Signal(ASID_WIDTH)
 103         self.content = PTE()
 104
 105     def flatten(self):
 106         return Cat(*self.ports())
 107
 108     def eq(self, x):
 109         return self.flatten().eq(x.flatten())
 110
 111     def ports(self):
 112         return [self.valid, self.is_2M, self.is_1G, self.vpn, self.asid] + \
 113                 self.content.ports()
 114
 115 # SV39 defines three levels of page tables
 116 LVL1 = Const(0, 2) # defined to 0 so that ptw_lvl default-resets to LVL1
 117 LVL2 = Const(1, 2)
 118 LVL3 = Const(2, 2)
 119
 120
 121 class PTW:
 122     def __init__(self):
 123         self.flush_i = Signal() # flush everything, we need to do this because
 124         # actually everything we do is speculative at this stage
 125         # e.g.: there could be a CSR instruction that changes everything
 126         self.ptw_active_o = Signal(reset=1)    # active if not IDLE
 127         self.walking_instr_o = Signal()        # set when walking for TLB
 128         self.ptw_error_o = Signal()            # set when an error occurred
 129         self.enable_translation_i = Signal()   # CSRs indicate to enable SV39
 130         self.en_ld_st_translation_i = Signal() # enable VM translation for ld/st
 131
 132         self.lsu_is_store_i = Signal()       # translation triggered by store
 133         # PTW memory interface
 134         self.req_port_i = DCacheReqO()
 135         self.req_port_o = DCacheReqI()
 136
 137         # to TLBs, update logic
 138         self.itlb_update_o = TLBUpdate()
 139         self.dtlb_update_o = TLBUpdate()
 140
 141         self.update_vaddr_o = Signal(39)
 142
 143         self.asid_i = Signal(ASID_WIDTH)
 144         # from TLBs
 145         # did we miss?
 146         self.itlb_access_i = Signal()
 147         self.itlb_hit_i = Signal()
 148         self.itlb_vaddr_i = Signal(64)
 149
 150         self.dtlb_access_i = Signal()
 151         self.dtlb_hit_i = Signal()
 152         self.dtlb_vaddr_i = Signal(64)
 153         # from CSR file
 154         self.satp_ppn_i = Signal(44) # ppn from satp
 155         self.mxr_i = Signal()
 156         # Performance counters
 157         self.itlb_miss_o = Signal()
 158         self.dtlb_miss_o = Signal()
 159
 160     def ports(self):
 161         return [self.ptw_active_o, self.walking_instr_o, self.ptw_error_o,
 162                 ]
 163         return [
 164                 self.enable_translation_i, self.en_ld_st_translation_i,
 165                 self.lsu_is_store_i, self.req_port_i, self.req_port_o,
 166                 self.update_vaddr_o,
 167                 self.asid_i,
 168                 self.itlb_access_i, self.itlb_hit_i, self.itlb_vaddr_i,
 169                 self.dtlb_access_i, self.dtlb_hit_i, self.dtlb_vaddr_i,
 170                 self.satp_ppn_i, self.mxr_i,
 171                 self.itlb_miss_o, self.dtlb_miss_o
 172             ] + self.itlb_update_o.ports() + self.dtlb_update_o.ports()
 173
 174     def elaborate(self, platform):
 175         m = Module()
 176
 177         # input registers
 178         data_rvalid = Signal()
 179         data_rdata = Signal(64)
 180
 181         pte = PTE()
 182         m.d.comb += pte.flatten().eq(data_rdata)
 183
 184         # SV39 defines three levels of page tables
 185         ptw_lvl = Signal(2) # default=0=LVL1
 186         ptw_lvl1 = Signal()
 187         ptw_lvl2 = Signal()
 188         ptw_lvl3 = Signal()
 189         m.d.comb += [ptw_lvl1.eq(ptw_lvl == LVL1),
 190                      ptw_lvl2.eq(ptw_lvl == LVL2),
 191                      ptw_lvl3.eq(ptw_lvl == LVL3)]
 192
 193         # is this an instruction page table walk?
 194         is_instr_ptw = Signal()
 195         global_mapping = Signal()
 196         # latched tag signal
 197         tag_valid = Signal()
 198         # register the ASID
 199         tlb_update_asid = Signal(ASID_WIDTH)
 200         # register VPN we need to walk, SV39 defines a 39 bit virtual addr
 201         vaddr = Signal(64)
 202         # 4 byte aligned physical pointer
 203         ptw_pptr = Signal(56)
 204
 205         end = DCACHE_INDEX_WIDTH + DCACHE_TAG_WIDTH
 206         m.d.sync += [
 207             # Assignments
 208             self.update_vaddr_o.eq(vaddr),
 209
 210             self.walking_instr_o.eq(is_instr_ptw),
 211             # directly output the correct physical address
 212             self.req_port_o.address_index.eq(ptw_pptr[0:DCACHE_INDEX_WIDTH]),
 213             self.req_port_o.address_tag.eq(ptw_pptr[DCACHE_INDEX_WIDTH:end]),
 214             # we are never going to kill this request
 215             self.req_port_o.kill_req.eq(0),              # XXX assign comb?
 216             # we are never going to write with the HPTW
 217             self.req_port_o.data_wdata.eq(Const(0, 64)), # XXX assign comb?
 218             # -----------
 219             # TLB Update
 220             # -----------
 221             self.itlb_update_o.vpn.eq(vaddr[12:39]),
 222             self.dtlb_update_o.vpn.eq(vaddr[12:39]),
 223             # update the correct page table level
 224             self.itlb_update_o.is_2M.eq(ptw_lvl2),
 225             self.itlb_update_o.is_1G.eq(ptw_lvl1),
 226             self.dtlb_update_o.is_2M.eq(ptw_lvl2),
 227             self.dtlb_update_o.is_1G.eq(ptw_lvl1),
 228             # output the correct ASID
 229             self.itlb_update_o.asid.eq(tlb_update_asid),
 230             self.dtlb_update_o.asid.eq(tlb_update_asid),
 231             # set the global mapping bit
 232             self.itlb_update_o.content.eq(pte),
 233             self.itlb_update_o.content.g.eq(global_mapping),
 234             self.dtlb_update_o.content.eq(pte),
 235             self.dtlb_update_o.content.g.eq(global_mapping),
 236
 237             self.req_port_o.tag_valid.eq(tag_valid),
 238         ]
 239
 240         #-------------------
 241         # Page table walker
 242         #-------------------
 243         # A virtual address va is translated into a physical address pa as
 244         # follows:
 245         # 1. Let a be sptbr.ppn × PAGESIZE, and let i = LEVELS-1. (For Sv39,
 246         #    PAGESIZE=2^12 and LEVELS=3.)
 247         # 2. Let pte be the value of the PTE at address a+va.vpn[i]×PTESIZE.
 248         #    (For Sv32, PTESIZE=4.)
 249         # 3. If pte.v = 0, or if pte.r = 0 and pte.w = 1, stop and raise an
 250         #    access exception.
 251         # 4. Otherwise, the PTE is valid. If pte.r = 1 or pte.x = 1, go to
 252         #    step 5.  Otherwise, this PTE is a pointer to the next level of
 253         #    the page table.
 254         #    Let i=i-1. If i < 0, stop and raise an access exception.
 255         #    Otherwise, let a = pte.ppn × PAGESIZE and go to step 2.
 256         # 5. A leaf PTE has been found. Determine if the requested memory
 257         #    access is allowed by the pte.r, pte.w, and pte.x bits. If not,
 258         #    stop and raise an access exception. Otherwise, the translation is
 259         #    successful.  Set pte.a to 1, and, if the memory access is a
 260         #    store, set pte.d to 1.
 261         #    The translated physical address is given as follows:
 262         #      - pa.pgoff = va.pgoff.
 263         #      - If i > 0, then this is a superpage translation and
 264         #        pa.ppn[i-1:0] = va.vpn[i-1:0].
 265         #      - pa.ppn[LEVELS-1:i] = pte.ppn[LEVELS-1:i].
 266         # 6. If i > 0 and pa.ppn[i − 1 : 0] != 0, this is a misaligned
 267         #    superpage stop and raise a page-fault exception.
 268
 269         m.d.sync += tag_valid.eq(0)
 270
 271         # default assignments
 272         m.d.comb += [
 273             # PTW memory interface
 274             self.req_port_o.data_req.eq(0),
 275             self.req_port_o.data_be.eq(Const(0xFF, 8)),
 276             self.req_port_o.data_size.eq(Const(0b11, 2)),
 277             self.req_port_o.data_we.eq(0),
 278             self.ptw_error_o.eq(0),
 279             self.itlb_update_o.valid.eq(0),
 280             self.dtlb_update_o.valid.eq(0),
 281
 282             self.itlb_miss_o.eq(0),
 283             self.dtlb_miss_o.eq(0),
 284         ]
 285
 286         # ------------
 287         # State Machine
 288         # ------------
 289
 290         with m.FSM() as fsm:
 291
 292             with m.State("IDLE"):
 293                 self.idle(m, is_instr_ptw, ptw_lvl, global_mapping,
 294                           ptw_pptr, vaddr, tlb_update_asid)
 295
 296             with m.State("WAIT_GRANT"):
 297                 self.grant(m, tag_valid, data_rvalid)
 298
 299             with m.State("PTE_LOOKUP"):
 300                 # we wait for the valid signal
 301                 with m.If(data_rvalid):
 302                     self.lookup(m, pte, ptw_lvl, ptw_lvl1, ptw_lvl2, ptw_lvl3,
 303                                 data_rvalid, global_mapping,
 304                                 is_instr_ptw, ptw_pptr)
 305
 306             # Propagate error to MMU/LSU
 307             with m.State("PROPAGATE_ERROR"):
 308                 m.next = "IDLE"
 309                 m.d.comb += self.ptw_error_o.eq(1)
 310
 311             # wait for the rvalid before going back to IDLE
 312             with m.State("WAIT_RVALID"):
 313                 with m.If(data_rvalid):
 314                     m.next = "IDLE"
 315
 316         m.d.sync += [data_rdata.eq(self.req_port_i.data_rdata),
 317                      data_rvalid.eq(self.req_port_i.data_rvalid)
 318                     ]
 319
 320         return m
 321
 322     def set_grant_state(self, m):
 323         # should we have flushed before we got an rvalid,
 324         # wait for it until going back to IDLE
 325         with m.If(self.flush_i):
 326             with m.If (self.req_port_i.data_gnt):
 327                 m.next = "WAIT_RVALID"
 328             with m.Else():
 329                 m.next = "IDLE"
 330         with m.Else():
 331             m.next = "WAIT_GRANT"
 332
 333     def idle(self, m, is_instr_ptw, ptw_lvl, global_mapping,
 334                           ptw_pptr, vaddr, tlb_update_asid):
 335         # by default we start with the top-most page table
 336         m.d.sync += [is_instr_ptw.eq(0),
 337                      ptw_lvl.eq(LVL1),
 338                      global_mapping.eq(0),
 339                      self.ptw_active_o.eq(0), # deactive (IDLE)
 340                     ]
 341         # work out itlb/dtlb miss
 342         m.d.comb += self.itlb_miss_o.eq(self.enable_translation_i & \
 343                                  self.itlb_access_i & \
 344                                  ~self.itlb_hit_i & \
 345                                  ~self.dtlb_access_i)
 346         m.d.comb += self.dtlb_miss_o.eq(self.en_ld_st_translation_i & \
 347                                         self.dtlb_access_i & \
 348                                         ~self.dtlb_hit_i)
 349         # we got an ITLB miss?
 350         with m.If(self.itlb_miss_o):
 351             pptr = Cat(Const(0, 3), self.itlb_vaddr_i[30:39],
 352                        self.satp_ppn_i)
 353             m.d.sync += [ptw_pptr.eq(pptr),
 354                          is_instr_ptw.eq(1),
 355                          vaddr.eq(self.itlb_vaddr_i),
 356                          tlb_update_asid.eq(self.asid_i),
 357                         ]
 358             self.set_grant_state(m)
 359
 360         # we got a DTLB miss?
 361         with m.Elif(self.dtlb_miss_o):
 362             pptr = Cat(Const(0, 3), self.dtlb_vaddr_i[30:39],
 363                        self.satp_ppn_i)
 364             m.d.sync += [ptw_pptr.eq(pptr),
 365                          vaddr.eq(self.dtlb_vaddr_i),
 366                          tlb_update_asid.eq(self.asid_i),
 367                         ]
 368             self.set_grant_state(m)
 369
 370     def grant(self, m, tag_valid, data_rvalid):
 371         # send a request out
 372         m.d.comb += self.req_port_o.data_req.eq(1)
 373         # wait for the WAIT_GRANT
 374         with m.If(self.req_port_i.data_gnt):
 375             # send the tag valid signal one cycle later
 376             m.d.sync += tag_valid.eq(1)
 377             # should we have flushed before we got an rvalid,
 378             # wait for it until going back to IDLE
 379             with m.If(self.flush_i):
 380                 with m.If (~data_rvalid):
 381                     m.next = "WAIT_RVALID"
 382                 with m.Else():
 383                     m.next = "IDLE"
 384             with m.Else():
 385                 m.next = "PTE_LOOKUP"
 386
 387     def lookup(self, m, pte, ptw_lvl, ptw_lvl1, ptw_lvl2, ptw_lvl3,
 388                             data_rvalid, global_mapping,
 389                             is_instr_ptw, ptw_pptr):
 390         # temporaries
 391         pte_rx = Signal(reset_less=True)
 392         pte_exe = Signal(reset_less=True)
 393         pte_inv = Signal(reset_less=True)
 394         a = Signal(reset_less=True)
 395         st_wd = Signal(reset_less=True)
 396         m.d.comb += [pte_rx.eq(pte.r | pte.x),
 397                     pte_exe.eq(~pte.x | ~pte.a),
 398                     pte_inv.eq(~pte.v | (~pte.r & pte.w)),
 399                     a.eq(pte.a & (pte.r | (pte.x & self.mxr_i))),
 400                     st_wd.eq(self.lsu_is_store_i & (~pte.w | ~pte.d))]
 401
 402         l1err = Signal(reset_less=True)
 403         l2err = Signal(reset_less=True)
 404         m.d.comb += [l2err.eq((ptw_lvl2) & pte.ppn[0:9] != Const(0, 9)),
 405                      l1err.eq((ptw_lvl1) & pte.ppn[0:18] != Const(0, 18)) ]
 406
 407         # check if the global mapping bit is set
 408         with m.If (pte.g):
 409             m.d.sync += global_mapping.eq(1)
 410
 411         # -------------
 412         # Invalid PTE
 413         # -------------
 414         # If pte.v = 0, or if pte.r = 0 and pte.w = 1,
 415         # stop and raise a page-fault exception.
 416         with m.If (pte_inv):
 417             m.next = "PROPAGATE_ERROR"
 418         # -----------
 419         # Valid PTE
 420         # -----------
 421         with m.Else():
 422             m.next = "IDLE"
 423             # it is a valid PTE
 424             # if pte.r = 1 or pte.x = 1 it is a valid PTE
 425             with m.If (pte_rx):
 426                 # Valid translation found (either 1G, 2M or 4K)
 427                 with m.If(is_instr_ptw):
 428                     # ------------
 429                     # Update ITLB
 430                     # ------------
 431                     # If page not executable, we can directly raise error.
 432                     # This doesn't put a useless entry into the TLB.
 433                     # The same idea applies to the access flag since we let
 434                     # the access flag be managed by SW.
 435                     with m.If (pte_exe):
 436                         m.next = "IDLE"
 437                     with m.Else():
 438                         m.d.comb += self.itlb_update_o.valid.eq(1)
 439
 440                 with m.Else():
 441                     # ------------
 442                     # Update DTLB
 443                     # ------------
 444                     # Check if the access flag has been set, otherwise
 445                     # throw page-fault and let software handle those bits.
 446                     # If page not readable (there are no write-only pages)
 447                     # directly raise an error. This doesn't put a useless
 448                     # entry into the TLB.
 449                     with m.If(a):
 450                         m.d.comb += self.dtlb_update_o.valid.eq(1)
 451                     with m.Else():
 452                         m.next = "PROPAGATE_ERROR"
 453                     # Request is a store: perform additional checks
 454                     # If the request was a store and the page not
 455                     # write-able, raise an error
 456                     # the same applies if the dirty flag is not set
 457                     with m.If (st_wd):
 458                         m.d.comb += self.dtlb_update_o.valid.eq(0)
 459                         m.next = "PROPAGATE_ERROR"
 460
 461                 # check if the ppn is correctly aligned: Case (6)
 462                 with m.If(l1err | l2err):
 463                     m.next = "PROPAGATE_ERROR"
 464                     m.d.comb += [self.dtlb_update_o.valid.eq(0),
 465                                  self.itlb_update_o.valid.eq(0)]
 466
 467             # this is a pointer to the next TLB level
 468             with m.Else():
 469                 # pointer to next level of page table
 470                 with m.If (ptw_lvl1):
 471                     # we are in the second level now
 472                     pptr = Cat(Const(0, 3), self.dtlb_vaddr_i[21:30], pte.ppn)
 473                     m.d.sync += [ptw_pptr.eq(pptr),
 474                                  ptw_lvl.eq(LVL2)
 475                                 ]
 476                 with m.If(ptw_lvl2):
 477                     # here we received a pointer to the third level
 478                     pptr = Cat(Const(0, 3), self.dtlb_vaddr_i[12:21], pte.ppn)
 479                     m.d.sync += [ptw_pptr.eq(pptr),
 480                                  ptw_lvl.eq(LVL3)
 481                                 ]
 482                 self.set_grant_state(m)
 483
 484                 with m.If (ptw_lvl3):
 485                     # Should already be the last level
 486                     # page table => Error
 487                     m.d.sync += ptw_lvl.eq(LVL3)
 488                     m.next = "PROPAGATE_ERROR"
 489
 490         # we've got a data WAIT_GRANT so tell the
 491         # cache that the tag is valid
 492
 493
 494 if __name__ == '__main__':
 495     ptw = PTW()
 496     vl = rtlil.convert(ptw, ports=ptw.ports())
 497     with open("test_ptw.il", "w") as f:
 498         f.write(vl)