TLB/src/ariane/ptw.py

   1 """
   2 # Copyright 2018 ETH Zurich and University of Bologna.
   3 # Copyright and related rights are licensed under the Solderpad Hardware
   4 # License, Version 0.51 (the "License"); you may not use this file except in
   5 # compliance with the License.  You may obtain a copy of the License at
   6 # http:#solderpad.org/licenses/SHL-0.51. Unless required by applicable law
   7 # or agreed to in writing, software, hardware and materials distributed under
   8 # this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
   9 # CONDITIONS OF ANY KIND, either express or implied. See the License for the
  10 # specific language governing permissions and limitations under the License.
  11 #
  12 # Author: David Schaffenrath, TU Graz
  13 # Author: Florian Zaruba, ETH Zurich
  14 # Date: 24.4.2017
  15 # Description: Hardware-PTW
  16
  17 /* verilator lint_off WIDTH */
  18 import ariane_pkg::*;
  19 """
  20
  21 class DCacheReqI:
  22     def __init__(self):
  23         self.address_index = Signal(DCACHE_INDEX_WIDTH)
  24         self.address_tag = Signal(DCACHE_TAG_WIDTH)
  25         self.data_wdata = Signal(64)
  26         self.data_req = Signal()
  27         self.data_we = Signal()
  28         self.data_be = Signal(8)
  29         self.data_size = Signal(2)
  30         self.kill_req = Signal()
  31         self.tag_valid = Signal()
  32
  33
  34 class DCacheReqO:
  35     def __init__(self):
  36         data_gnt = Signal()
  37         data_rvalid = Signal()
  38         data_rdata = Signal(64)
  39
  40 ASID_WIDTH = 1
  41
  42 class PTE(RecordObject):
  43     def __init__(self):
  44         self.reserved = Signal(10)
  45         self.ppn = Signal(44)
  46         self.rsw = Signal(2)
  47         self.d = Signal()
  48         self.a = Signal()
  49         self.g = Signal()
  50         self.u = Signal()
  51         self.x = Signal()
  52         self.w = Signal()
  53         self.r = Signal()
  54         self.v = Signal()
  55
  56
  57 class TLBUpdate:
  58     def __init__(self):
  59         valid = Signal()      # valid flag
  60         is_2M = Signal()
  61         is_1G = Signal()
  62         vpn = Signal(27)
  63         asid = Signal(ASID_WIDTH)
  64         content = PTE()
  65
  66 IDLE = 0
  67 WAIT_GRANT = 1
  68 PTE_LOOKUP = 2
  69 WAIT_RVALID = 3
  70 PROPAGATE_ERROR = 4
  71
  72 # SV39 defines three levels of page tables
  73 LVL1 = Const(0, 2)
  74 LVL2 = Const(1, 2)
  75 LVL3 = Const(2, 2)
  76
  77
  78 class PTW:
  79     flush_i = Signal() # flush everything, we need to do this because
  80     # actually everything we do is speculative at this stage
  81     # e.g.: there could be a CSR instruction that changes everything
  82     ptw_active_o = Signal()
  83     walking_instr_o = Signal()        # set when walking for TLB
  84     ptw_error_o = Signal()            # set when an error occurred
  85     enable_translation_i = Signal()   # CSRs indicate to enable SV39
  86     en_ld_st_translation_i = Signal() # enable VM translation for load/stores
  87
  88     lsu_is_store_i = Signal() ,       # this translation triggered by a store
  89     # PTW memory interface
  90     req_port_i = DCacheReqO()
  91     req_port_o = DCacheReqI()
  92
  93     # to TLBs, update logic
  94     itlb_update_o = TLBUpdate()
  95     dtlb_update_o = TLBUpdate()
  96
  97     update_vaddr_o = Signal(39)
  98
  99     asid_i = Signal(ASID_WIDTH)
 100     # from TLBs
 101     # did we miss?
 102     itlb_access_i = Signal()
 103     itlb_hit_i = Signal()
 104     itlb_vaddr_i = Signal(64)
 105
 106     dtlb_access_i = Signal()
 107     dtlb_hit_i = Signal()
 108     dtlb_vaddr_i = Signal(64)
 109     # from CSR file
 110     satp_ppn_i = Signal(44) # ppn from satp
 111     mxr_i = Signal()
 112     # Performance counters
 113     itlb_miss_o = Signal()
 114     dtlb_miss_o = Signal()
 115
 116 );
 117
 118     # input registers
 119     data_rvalid_q = Signal()
 120     data_rdata_q = Signal(64)
 121
 122     pte = PTE()
 123     assign pte = riscv::pte_t(data_rdata_q);
 124
 125     # is this an instruction page table walk?
 126     is_instr_ptw_q = Signal()
 127     is_instr_ptw_n = Signal()
 128     global_mapping_q = Signal()
 129     global_mapping_n = Signal()
 130     # latched tag signal
 131     tag_valid_n = Signal()
 132     tag_valid_q = Signal()
 133     # register the ASID
 134     tlb_update_asid_q = Signal(ASID_WIDTH)
 135     tlb_update_asid_n = Signal(ASID_WIDTH)
 136     # register the VPN we need to walk, SV39 defines a 39 bit virtual address
 137     vaddr_q = Signal(64)
 138     vaddr_n = Signal(64)
 139     # 4 byte aligned physical pointer
 140     ptw_pptr_q = Signal(56)
 141     ptw_pptr_n = Signal(56)
 142
 143     # Assignments
 144     m.d.comb += update_vaddr_o.eq(vaddr_q)
 145
 146     m.d.comb += ptw_active_o.eq(state_q != IDLE)
 147     m.d.comb += walking_instr_o.eq(is_instr_ptw_q)
 148     # directly output the correct physical address
 149     m.d.comb += req_port_o.address_index.eq(ptw_pptr_q[0:DCACHE_INDEX_WIDTH])
 150     end = DCACHE_INDEX_WIDTH + DCACHE_TAG_WIDTH
 151     m.d.comb += req_port_o.address_tag.eq(ptw_pptr_q[DCACHE_INDEX_WIDTH:end])
 152     # we are never going to kill this request
 153     m.d.comb += req_port_o.kill_req.eq(0)
 154     # we are never going to write with the HPTW
 155     m.d.comb += req_port_o.data_wdata.eq(Const(0, 64))
 156     # -----------
 157     # TLB Update
 158     # -----------
 159     assign itlb_update_o.vpn = vaddr_q[38:12];
 160     assign dtlb_update_o.vpn = vaddr_q[38:12];
 161     # update the correct page table level
 162     assign itlb_update_o.is_2M = (ptw_lvl_q == LVL2);
 163     assign itlb_update_o.is_1G = (ptw_lvl_q == LVL1);
 164     assign dtlb_update_o.is_2M = (ptw_lvl_q == LVL2);
 165     assign dtlb_update_o.is_1G = (ptw_lvl_q == LVL1);
 166     # output the correct ASID
 167     assign itlb_update_o.asid = tlb_update_asid_q;
 168     assign dtlb_update_o.asid = tlb_update_asid_q;
 169     # set the global mapping bit
 170     assign itlb_update_o.content = pte | (global_mapping_q << 5);
 171     assign dtlb_update_o.content = pte | (global_mapping_q << 5);
 172
 173     assign req_port_o.tag_valid      = tag_valid_q;
 174
 175     #-------------------
 176     # Page table walker
 177     #-------------------
 178     # A virtual address va is translated into a physical address pa as follows:
 179     # 1. Let a be sptbr.ppn × PAGESIZE, and let i = LEVELS-1. (For Sv39,
 180     #    PAGESIZE=2^12 and LEVELS=3.)
 181     # 2. Let pte be the value of the PTE at address a+va.vpn[i]×PTESIZE. (For
 182     #    Sv32, PTESIZE=4.)
 183     # 3. If pte.v = 0, or if pte.r = 0 and pte.w = 1, stop and raise an access
 184     #    exception.
 185     # 4. Otherwise, the PTE is valid. If pte.r = 1 or pte.x = 1, go to step 5.
 186     #    Otherwise, this PTE is a pointer to the next level of the page table.
 187     #    Let i=i-1. If i < 0, stop and raise an access exception. Otherwise, let
 188     #    a = pte.ppn × PAGESIZE and go to step 2.
 189     # 5. A leaf PTE has been found. Determine if the requested memory access
 190     #    is allowed by the pte.r, pte.w, and pte.x bits. If not, stop and
 191     #    raise an access exception. Otherwise, the translation is successful.
 192     #    Set pte.a to 1, and, if the memory access is a store, set pte.d to 1.
 193     #    The translated physical address is given as follows:
 194     #      - pa.pgoff = va.pgoff.
 195     #      - If i > 0, then this is a superpage translation and
 196     #        pa.ppn[i-1:0] = va.vpn[i-1:0].
 197     #      - pa.ppn[LEVELS-1:i] = pte.ppn[LEVELS-1:i].
 198     always_comb begin : ptw
 199         # default assignments
 200         # PTW memory interface
 201         tag_valid_n           = 1'b0;
 202         req_port_o.data_req   = 1'b0;
 203         req_port_o.data_be    = 8'hFF;
 204         req_port_o.data_size  = 2'b11;
 205         req_port_o.data_we    = 1'b0;
 206         ptw_error_o           = 1'b0;
 207         itlb_update_o.valid   = 1'b0;
 208         dtlb_update_o.valid   = 1'b0;
 209         is_instr_ptw_n        = is_instr_ptw_q;
 210         ptw_lvl_n             = ptw_lvl_q;
 211         ptw_pptr_n            = ptw_pptr_q;
 212         state_d               = state_q;
 213         global_mapping_n      = global_mapping_q;
 214         # input registers
 215         tlb_update_asid_n     = tlb_update_asid_q;
 216         vaddr_n               = vaddr_q;
 217
 218         itlb_miss_o           = 1'b0;
 219         dtlb_miss_o           = 1'b0;
 220
 221         case (state_q)
 222
 223             IDLE: begin
 224                 # by default we start with the top-most page table
 225                 ptw_lvl_n        = LVL1;
 226                 global_mapping_n = 1'b0;
 227                 is_instr_ptw_n   = 1'b0;
 228                 # if we got an ITLB miss
 229                 if (enable_translation_i & itlb_access_i & ~itlb_hit_i & ~dtlb_access_i) begin
 230                     ptw_pptr_n          = {satp_ppn_i, itlb_vaddr_i[38:30], 3'b0};
 231                     is_instr_ptw_n      = 1'b1;
 232                     tlb_update_asid_n   = asid_i;
 233                     vaddr_n             = itlb_vaddr_i;
 234                     state_d             = WAIT_GRANT;
 235                     itlb_miss_o         = 1'b1;
 236                 # we got an DTLB miss
 237                 end else if (en_ld_st_translation_i & dtlb_access_i & ~dtlb_hit_i) begin
 238                     ptw_pptr_n          = {satp_ppn_i, dtlb_vaddr_i[38:30], 3'b0};
 239                     tlb_update_asid_n   = asid_i;
 240                     vaddr_n             = dtlb_vaddr_i;
 241                     state_d             = WAIT_GRANT;
 242                     dtlb_miss_o         = 1'b1;
 243                 end
 244             end
 245
 246             WAIT_GRANT: begin
 247                 # send a request out
 248                 req_port_o.data_req = 1'b1;
 249                 # wait for the WAIT_GRANT
 250                 if (req_port_i.data_gnt) begin
 251                     # send the tag valid signal one cycle later
 252                     tag_valid_n = 1'b1;
 253                     state_d     = PTE_LOOKUP;
 254                 end
 255             end
 256
 257             PTE_LOOKUP: begin
 258                 # we wait for the valid signal
 259                 if (data_rvalid_q) begin
 260
 261                     # check if the global mapping bit is set
 262                     if (pte.g)
 263                         global_mapping_n = 1'b1;
 264
 265                     # -------------
 266                     # Invalid PTE
 267                     # -------------
 268                     # If pte.v = 0, or if pte.r = 0 and pte.w = 1, stop and raise a page-fault exception.
 269                     if (!pte.v || (!pte.r && pte.w))
 270                         state_d = PROPAGATE_ERROR;
 271                     # -----------
 272                     # Valid PTE
 273                     # -----------
 274                     else begin
 275                         state_d = IDLE;
 276                         # it is a valid PTE
 277                         # if pte.r = 1 or pte.x = 1 it is a valid PTE
 278                         if (pte.r || pte.x) begin
 279                             # Valid translation found (either 1G, 2M or 4K entry)
 280                             if (is_instr_ptw_q) begin
 281                                 # ------------
 282                                 # Update ITLB
 283                                 # ------------
 284                                 # If page is not executable, we can directly raise an error. This
 285                                 # doesn't put a useless entry into the TLB. The same idea applies
 286                                 # to the access flag since we let the access flag be managed by SW.
 287                                 if (!pte.x || !pte.a)
 288                                   state_d = PROPAGATE_ERROR;
 289                                 else
 290                                   itlb_update_o.valid = 1'b1;
 291
 292                             end else begin
 293                                 # ------------
 294                                 # Update DTLB
 295                                 # ------------
 296                                 # Check if the access flag has been set, otherwise throw a page-fault
 297                                 # and let the software handle those bits.
 298                                 # If page is not readable (there are no write-only pages)
 299                                 # we can directly raise an error. This doesn't put a useless
 300                                 # entry into the TLB.
 301                                 if (pte.a && (pte.r || (pte.x && mxr_i))) begin
 302                                   dtlb_update_o.valid = 1'b1;
 303                                 end else begin
 304                                   state_d   = PROPAGATE_ERROR;
 305                                 end
 306                                 # Request is a store: perform some additional checks
 307                                 # If the request was a store and the page is not write-able, raise an error
 308                                 # the same applies if the dirty flag is not set
 309                                 if (lsu_is_store_i && (!pte.w || !pte.d)) begin
 310                                     dtlb_update_o.valid = 1'b0;
 311                                     state_d   = PROPAGATE_ERROR;
 312                                 end
 313                             end
 314                             # check if the ppn is correctly aligned:
 315                             # 6. If i > 0 and pa.ppn[i − 1 : 0] != 0, this is a misaligned superpage; stop and raise a page-fault
 316                             # exception.
 317                             if (ptw_lvl_q == LVL1 && pte.ppn[17:0] != '0) begin
 318                                 state_d             = PROPAGATE_ERROR;
 319                                 dtlb_update_o.valid = 1'b0;
 320                                 itlb_update_o.valid = 1'b0;
 321                             end else if (ptw_lvl_q == LVL2 && pte.ppn[8:0] != '0) begin
 322                                 state_d             = PROPAGATE_ERROR;
 323                                 dtlb_update_o.valid = 1'b0;
 324                                 itlb_update_o.valid = 1'b0;
 325                             end
 326                         # this is a pointer to the next TLB level
 327                         end else begin
 328                             # pointer to next level of page table
 329                             if (ptw_lvl_q == LVL1) begin
 330                                 # we are in the second level now
 331                                 ptw_lvl_n  = LVL2;
 332                                 ptw_pptr_n = {pte.ppn, vaddr_q[29:21], 3'b0};
 333                             end
 334
 335                             if (ptw_lvl_q == LVL2) begin
 336                                 # here we received a pointer to the third level
 337                                 ptw_lvl_n  = LVL3;
 338                                 ptw_pptr_n = {pte.ppn, vaddr_q[20:12], 3'b0};
 339                             end
 340
 341                             state_d = WAIT_GRANT;
 342
 343                             if (ptw_lvl_q == LVL3) begin
 344                               # Should already be the last level page table => Error
 345                               ptw_lvl_n   = LVL3;
 346                               state_d = PROPAGATE_ERROR;
 347                             end
 348                         end
 349                     end
 350                 end
 351                 # we've got a data WAIT_GRANT so tell the cache that the tag is valid
 352             end
 353             # Propagate error to MMU/LSU
 354             PROPAGATE_ERROR: begin
 355                 state_d     = IDLE;
 356                 ptw_error_o = 1'b1;
 357             end
 358             # wait for the rvalid before going back to IDLE
 359             WAIT_RVALID: begin
 360                 if (data_rvalid_q)
 361                     state_d = IDLE;
 362             end
 363             default: begin
 364                 state_d = IDLE;
 365             end
 366         endcase
 367
 368         # -------
 369         # Flush
 370         # -------
 371         # should we have flushed before we got an rvalid, wait for it until going back to IDLE
 372         if (flush_i) begin
 373             # on a flush check whether we are
 374             # 1. in the PTE Lookup check whether we still need to wait for an rvalid
 375             # 2. waiting for a grant, if so: wait for it
 376             # if not, go back to idle
 377             if ((state_q == PTE_LOOKUP && !data_rvalid_q) || ((state_q == WAIT_GRANT) && req_port_i.data_gnt))
 378                 state_d = WAIT_RVALID;
 379             else
 380                 state_d = IDLE;
 381         end
 382     end
 383
 384     # sequential process
 385     always_ff @(posedge clk_i or negedge rst_ni) begin
 386         if (~rst_ni) begin
 387             state_q            <= IDLE;
 388             is_instr_ptw_q     <= 1'b0;
 389             ptw_lvl_q          <= LVL1;
 390             tag_valid_q        <= 1'b0;
 391             tlb_update_asid_q  <= '0;
 392             vaddr_q            <= '0;
 393             ptw_pptr_q         <= '0;
 394             global_mapping_q   <= 1'b0;
 395             data_rdata_q       <= '0;
 396             data_rvalid_q      <= 1'b0;
 397         end else begin
 398             state_q            <= state_d;
 399             ptw_pptr_q         <= ptw_pptr_n;
 400             is_instr_ptw_q     <= is_instr_ptw_n;
 401             ptw_lvl_q          <= ptw_lvl_n;
 402             tag_valid_q        <= tag_valid_n;
 403             tlb_update_asid_q  <= tlb_update_asid_n;
 404             vaddr_q            <= vaddr_n;
 405             global_mapping_q   <= global_mapping_n;
 406             data_rdata_q       <= req_port_i.data_rdata;
 407             data_rvalid_q      <= req_port_i.data_rvalid;
 408         end
 409     end
 410
 411 endmodule
 412 /* verilator lint_on WIDTH */