TLB/src/ariane/tlb.py

   1 """
   2 # Copyright 2018 ETH Zurich and University of Bologna.
   3 # Copyright and related rights are licensed under the Solderpad Hardware
   4 # License, Version 0.51 (the "License"); you may not use this file except in
   5 # compliance with the License.  You may obtain a copy of the License at
   6 # http:#solderpad.org/licenses/SHL-0.51. Unless required by applicable law
   7 # or agreed to in writing, software, hardware and materials distributed under
   8 # this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
   9 # CONDITIONS OF ANY KIND, either express or implied. See the License for the
  10 # specific language governing permissions and limitations under the License.
  11 #
  12 # Author: David Schaffenrath, TU Graz
  13 # Author: Florian Zaruba, ETH Zurich
  14 # Date: 21.4.2017
  15 # Description: Translation Lookaside Buffer, SV39
  16 #              fully set-associative
  17 """
  18 from math import log2
  19 from nmigen import Signal, Module, Cat, Const, Array
  20 from nmigen.cli import verilog, rtlil
  21
  22
  23 # SV39 defines three levels of page tables
  24 class TLBEntry:
  25     def __init__(self):
  26         self.asid = Signal(ASID_WIDTH)
  27         self.vpn2 = Signal(9)
  28         self.vpn1 = Signal(9)
  29         self.vpn0 = Signal(9)
  30         self.is_2M = Signal()
  31         self.is_1G = Signal()
  32         self.valid = Signal()
  33
  34 TLB_ENTRIES = 4
  35 ASID_WIDTH  = 1
  36
  37 from ptw import TLBUpdate, PTE
  38
  39
  40 class TLB:
  41     def __init__(self):
  42         self.flush_i = Signal()  # Flush signal
  43         # Update TLB
  44         self.update_i = TLBUpdate()
  45         # Lookup signals
  46         self.lu_access_i = Signal()
  47         self.lu_asid_i = Signal(ASID_WIDTH)
  48         self.lu_vaddr_i = Signal(64)
  49         self.lu_content_o = PTE()
  50         self.lu_is_2M_o = Signal()
  51         self.lu_is_1G_o = Signal()
  52         self.lu_hit_o = Signal()
  53
  54     def elaborate(self, platform):
  55         m = Module()
  56
  57         # SV39 defines three levels of page tables
  58         tags = Array([TLBEntry() for i in range(TLB_ENTRIES)])
  59         content = Array([PTE() for i in range(TLB_ENTRIES)])
  60
  61         vpn2 = Signal(9)
  62         vpn1 = Signal(9)
  63         vpn0 = Signal(9)
  64         lu_hit = Signal(TLB_ENTRIES)     # to replacement logic
  65         replace_en = Signal(TLB_ENTRIES) # replace the following entry,
  66                                          # set by replacement strategy
  67         #-------------
  68         # Translation
  69         #-------------
  70         m.d.comb += [ vpn0.eq(self.lu_vaddr_i[12:21]),
  71                       vpn1.eq(self.lu_vaddr_i[21:30]),
  72                       vpn2.eq(self.lu_vaddr_i[30:39]),
  73                     ]
  74
  75         for i in range(TLB_ENTRIES):
  76             m.d.comb += lu_hit[i].eq(0)
  77             # first level match, this may be a giga page,
  78             # check the ASID flags as well
  79             asid_ok = Signal()
  80             vpn2_ok = Signal()
  81             tags_ok = Signal()
  82             l2_hit = Signal()
  83             m.d.comb += [tags_ok.eq(tags[i].valid),
  84                          asid_ok.eq(tags[i].asid == self.lu_asid_i),
  85                          vpn2_ok.eq(tags[i].vpn2 == vpn2),
  86                          l2_hit.eq(tags_ok & asid_ok & vpn2_ok)]
  87             with m.If(l2_hit):
  88                 # second level
  89                 with m.If (tags[i].is_1G):
  90                     m.d.sync += self.lu_content_o.eq(content[i])
  91                     m.d.comb += [ self.lu_is_1G_o.eq(1),
  92                                   self.lu_hit_o.eq(1),
  93                                   lu_hit[i].eq(1),
  94                                 ]
  95                 # not a giga page hit so check further
  96                 with m.Elif(vpn1 == tags[i].vpn1):
  97                     # this could be a 2 mega page hit or a 4 kB hit
  98                     # output accordingly
  99                     with m.If(tags[i].is_2M | (vpn0 == tags[i].vpn0)):
 100                         m.d.sync += self.lu_content_o.eq(content[i])
 101                         m.d.comb += [ self.lu_is_2M_o.eq(tags[i].is_2M),
 102                                       self.lu_hit_o.eq(1),
 103                                       lu_hit[i].eq(1),
 104                                     ]
 105
 106         # ------------------
 107         # Update and Flush
 108         # ------------------
 109
 110         for i in range(TLB_ENTRIES):
 111             with m.If (self.flush_i):
 112                 # invalidate (flush) conditions: all if zero or just this ASID
 113                 with m.If (self.lu_asid_i == Const(0, ASID_WIDTH) |
 114                           (self.lu_asid_i == tags[i].asid)):
 115                     m.d.sync += tags[i].valid.eq(0)
 116
 117             # normal replacement
 118             with m.Elif(self.update_i.valid & replace_en[i]):
 119                 m.d.sync += [ # update tag array
 120                               tags[i].asid.eq(self.update_i.asid),
 121                               tags[i].vpn2.eq(self.update_i.vpn[18:27]),
 122                               tags[i].vpn1.eq(self.update_i.vpn[9:18]),
 123                               tags[i].vpn0.eq(self.update_i.vpn[0:9]),
 124                               tags[i].is_1G.eq(self.update_i.is_1G),
 125                               tags[i].is_2M.eq(self.update_i.is_2M),
 126                               tags[i].valid.eq(1),
 127                               # and content as well
 128                               content[i].eq(self.update_i.content)
 129                             ]
 130
 131         # -----------------------------------------------
 132         # PLRU - Pseudo Least Recently Used Replacement
 133         # -----------------------------------------------
 134
 135         TLBSZ = 2*(TLB_ENTRIES-1)
 136         plru_tree = Signal(TLBSZ)
 137
 138         # The PLRU-tree indexing:
 139         # lvl0        0
 140         #            / \
 141         #           /   \
 142         # lvl1     1     2
 143         #         / \   / \
 144         # lvl2   3   4 5   6
 145         #       / \ /\/\  /\
 146         #      ... ... ... ...
 147         # Just predefine which nodes will be set/cleared
 148         # E.g. for a TLB with 8 entries, the for-loop is semantically
 149         # equivalent to the following pseudo-code:
 150         # unique case (1'b1)
 151         # lu_hit[7]: plru_tree[0, 2, 6] = {1, 1, 1};
 152         # lu_hit[6]: plru_tree[0, 2, 6] = {1, 1, 0};
 153         # lu_hit[5]: plru_tree[0, 2, 5] = {1, 0, 1};
 154         # lu_hit[4]: plru_tree[0, 2, 5] = {1, 0, 0};
 155         # lu_hit[3]: plru_tree[0, 1, 4] = {0, 1, 1};
 156         # lu_hit[2]: plru_tree[0, 1, 4] = {0, 1, 0};
 157         # lu_hit[1]: plru_tree[0, 1, 3] = {0, 0, 1};
 158         # lu_hit[0]: plru_tree[0, 1, 3] = {0, 0, 0};
 159         # default: begin /* No hit */ end
 160         # endcase
 161         LOG_TLB = int(log2(TLB_ENTRIES))
 162         for i in range(TLB_ENTRIES):
 163             # we got a hit so update the pointer as it was least recently used
 164             with m.If (lu_hit[i] & self.lu_access_i):
 165                 # Set the nodes to the values we would expect
 166                 for lvl in range(LOG_TLB):
 167                     idx_base = (1<<lvl)-1
 168                     # lvl0 <=> MSB, lvl1 <=> MSB-1, ...
 169                     shift = LOG_TLB - lvl;
 170                     new_idx = Const(~((i >> (shift-1)) & 1), 1)
 171                     print ("plru", i, lvl, hex(idx_base), shift, new_idx)
 172                     m.d.sync += plru_tree[idx_base + (i >> shift)].eq(new_idx)
 173
 174         # Decode tree to write enable signals
 175         # Next for-loop basically creates the following logic for e.g.
 176         # an 8 entry TLB (note: pseudo-code obviously):
 177         # replace_en[7] = &plru_tree[ 6, 2, 0]; #plru_tree[0,2,6]=={1,1,1}
 178         # replace_en[6] = &plru_tree[~6, 2, 0]; #plru_tree[0,2,6]=={1,1,0}
 179         # replace_en[5] = &plru_tree[ 5,~2, 0]; #plru_tree[0,2,5]=={1,0,1}
 180         # replace_en[4] = &plru_tree[~5,~2, 0]; #plru_tree[0,2,5]=={1,0,0}
 181         # replace_en[3] = &plru_tree[ 4, 1,~0]; #plru_tree[0,1,4]=={0,1,1}
 182         # replace_en[2] = &plru_tree[~4, 1,~0]; #plru_tree[0,1,4]=={0,1,0}
 183         # replace_en[1] = &plru_tree[ 3,~1,~0]; #plru_tree[0,1,3]=={0,0,1}
 184         # replace_en[0] = &plru_tree[~3,~1,~0]; #plru_tree[0,1,3]=={0,0,0}
 185         # For each entry traverse the tree. If every tree-node matches
 186         # the corresponding bit of the entry's index, this is
 187         # the next entry to replace.
 188         for i in range(TLB_ENTRIES):
 189             en = [Const(1)]
 190             for lvl in range(LOG_TLB):
 191                 idx_base = (1<<lvl)-1
 192                 # lvl0 <=> MSB, lvl1 <=> MSB-1, ...
 193                 shift = LOG_TLB - lvl;
 194                 new_idx = (i >> (shift-1)) & 1;
 195                 plru = Signal(1)
 196                 m.d.comb += plru.eq(plru_tree[idx_base + (i>>shift)])
 197                 # en &= plru_tree_q[idx_base + (i>>shift)] == new_idx;
 198                 if new_idx:
 199                     en.append(~plru) # yes inverted (using bool())
 200                 else:
 201                     en.append(plru)  # yes inverted (using bool())
 202             print ("plru", i, en)
 203             # boolean logic manipluation:
 204             # plur0 & plru1 & plur2 == ~(~plru0 | ~plru1 | ~plru2)
 205             m.d.sync += replace_en[i].eq(~Cat(*en).bool())
 206
 207         #--------------
 208         # Sanity checks
 209         #--------------
 210
 211         assert (TLB_ENTRIES % 2 == 0) and (TLB_ENTRIES > 1), \
 212             "TLB size must be a multiple of 2 and greater than 1"
 213         assert (ASID_WIDTH >= 1), \
 214             "ASID width must be at least 1"
 215
 216         return m
 217
 218         """
 219         # Just for checking
 220         function int countSetBits(logic[TLB_ENTRIES-1:0] vector);
 221           automatic int count = 0;
 222           foreach (vector[idx]) begin
 223             count += vector[idx];
 224           end
 225           return count;
 226         endfunction
 227
 228         assert property (@(posedge clk_i)(countSetBits(lu_hit) <= 1))
 229           else $error("More then one hit in TLB!"); $stop(); end
 230         assert property (@(posedge clk_i)(countSetBits(replace_en) <= 1))
 231           else $error("More then one TLB entry selected for next replace!");
 232         """
 233
 234     def ports(self):
 235         return [self.flush_i, self.lu_access_i,
 236                  self.lu_asid_i, self.lu_vaddr_i,
 237                  self.lu_is_2M_o, self.lu_is_1G_o, self.lu_hit_o,
 238                 ] + self.lu_content_o.ports() + self.update_i.ports()
 239
 240 if __name__ == '__main__':
 241     tlb = TLB()
 242     vl = rtlil.convert(tlb, ports=tlb.ports())
 243     with open("test_tlb.il", "w") as f:
 244         f.write(vl)
 245