TLB/src/ariane/tlb.py

   1 """
   2 # Copyright 2018 ETH Zurich and University of Bologna.
   3 # Copyright and related rights are licensed under the Solderpad Hardware
   4 # License, Version 0.51 (the "License"); you may not use this file except in
   5 # compliance with the License.  You may obtain a copy of the License at
   6 # http:#solderpad.org/licenses/SHL-0.51. Unless required by applicable law
   7 # or agreed to in writing, software, hardware and materials distributed under
   8 # this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
   9 # CONDITIONS OF ANY KIND, either express or implied. See the License for the
  10 # specific language governing permissions and limitations under the License.
  11 #
  12 # Author: David Schaffenrath, TU Graz
  13 # Author: Florian Zaruba, ETH Zurich
  14 # Date: 21.4.2017
  15 # Description: Translation Lookaside Buffer, SV39
  16 #              fully set-associative
  17 """
  18 from math import log2
  19 from nmigen import Signal, Module, Cat, Const, Array
  20 from nmigen.cli import verilog, rtlil
  21
  22
  23 # SV39 defines three levels of page tables
  24 class TLBEntry:
  25     def __init__(self):
  26         self.asid = Signal(ASID_WIDTH)
  27         self.vpn2 = Signal(9)
  28         self.vpn1 = Signal(9)
  29         self.vpn0 = Signal(9)
  30         self.is_2M = Signal()
  31         self.is_1G = Signal()
  32         self.valid = Signal()
  33
  34 TLB_ENTRIES = 4
  35 ASID_WIDTH  = 1
  36
  37 from ptw import TLBUpdate, PTE
  38
  39
  40 class TLB:
  41     def __init__(self):
  42         self.flush_i = Signal()  # Flush signal
  43         # Update TLB
  44         self.update_i = TLBUpdate()
  45         # Lookup signals
  46         self.lu_access_i = Signal()
  47         self.lu_asid_i = Signal(ASID_WIDTH)
  48         self.lu_vaddr_i = Signal(64)
  49         self.lu_content_o = PTE()
  50         self.lu_is_2M_o = Signal()
  51         self.lu_is_1G_o = Signal()
  52         self.lu_hit_o = Signal()
  53
  54     def elaborate(self, platform):
  55         m = Module()
  56
  57         # SV39 defines three levels of page tables
  58         tags = Array([TLBEntry() for i in range(TLB_ENTRIES)])
  59         content = Array([PTE() for i in range(TLB_ENTRIES)])
  60
  61         vpn2 = Signal(9)
  62         vpn1 = Signal(9)
  63         vpn0 = Signal(9)
  64         lu_hit = Signal(TLB_ENTRIES)     # to replacement logic
  65         replace_en = Signal(TLB_ENTRIES) # replace the following entry,
  66                                          # set by replacement strategy
  67         #-------------
  68         # Translation
  69         #-------------
  70         m.d.comb += [ vpn0.eq(self.lu_vaddr_i[12:21]),
  71                       vpn1.eq(self.lu_vaddr_i[21:30]),
  72                       vpn2.eq(self.lu_vaddr_i[30:39]),
  73                     ]
  74
  75         for i in range(TLB_ENTRIES):
  76             m.d.comb += lu_hit[i].eq(0)
  77             # first level match, this may be a giga page,
  78             # check the ASID flags as well
  79             with m.If(tags[i].valid & \
  80                       (tags[i].asid == self.lu_asid_i) &  \
  81                       (tags[i].vpn2 == vpn2)):
  82                 # second level
  83                 with m.If (tags[i].is_1G):
  84                     m.d.sync += self.lu_content_o.eq(content[i])
  85                     m.d.comb += [ self.lu_is_1G_o.eq(1),
  86                                   self.lu_hit_o.eq(1),
  87                                   lu_hit[i].eq(1),
  88                                 ]
  89                 # not a giga page hit so check further
  90                 with m.Elif(vpn1 == tags[i].vpn1):
  91                     # this could be a 2 mega page hit or a 4 kB hit
  92                     # output accordingly
  93                     with m.If(tags[i].is_2M | (vpn0 == tags[i].vpn0)):
  94                         m.d.sync += self.lu_content_o.eq(content[i])
  95                         m.d.comb += [ self.lu_is_2M_o.eq(tags[i].is_2M),
  96                                       self.lu_hit_o.eq(1),
  97                                       lu_hit[i].eq(1),
  98                                     ]
  99
 100         # ------------------
 101         # Update and Flush
 102         # ------------------
 103
 104         for i in range(TLB_ENTRIES):
 105             with m.If (self.flush_i):
 106                 # invalidate (flush) conditions: all if zero or just this ASID
 107                 with m.If (self.lu_asid_i == Const(0, ASID_WIDTH) |
 108                           (self.lu_asid_i == tags[i].asid)):
 109                     m.d.sync += tags[i].valid.eq(0)
 110
 111             # normal replacement
 112             with m.Elif(self.update_i.valid & replace_en[i]):
 113                 m.d.sync += [ # update tag array
 114                               tags[i].asid.eq(self.update_i.asid),
 115                               tags[i].vpn2.eq(self.update_i.vpn [18:27]),
 116                               tags[i].vpn1.eq(self.update_i.vpn [9:18]),
 117                               tags[i].vpn0.eq(self.update_i.vpn[0:9]),
 118                               tags[i].is_1G.eq(self.update_i.is_1G),
 119                               tags[i].is_2M.eq(self.update_i.is_2M),
 120                               tags[i].valid.eq(1),
 121                               # and content as well
 122                               content[i].eq(self.update_i.content)
 123                             ]
 124
 125         # -----------------------------------------------
 126         # PLRU - Pseudo Least Recently Used Replacement
 127         # -----------------------------------------------
 128
 129         TLBSZ = 2*(TLB_ENTRIES-1)
 130         plru_tree = Signal(TLBSZ)
 131
 132         # The PLRU-tree indexing:
 133         # lvl0        0
 134         #            / \
 135         #           /   \
 136         # lvl1     1     2
 137         #         / \   / \
 138         # lvl2   3   4 5   6
 139         #       / \ /\/\  /\
 140         #      ... ... ... ...
 141         # Just predefine which nodes will be set/cleared
 142         # E.g. for a TLB with 8 entries, the for-loop is semantically
 143         # equivalent to the following pseudo-code:
 144         # unique case (1'b1)
 145         # lu_hit[7]: plru_tree[0, 2, 6] = {1, 1, 1};
 146         # lu_hit[6]: plru_tree[0, 2, 6] = {1, 1, 0};
 147         # lu_hit[5]: plru_tree[0, 2, 5] = {1, 0, 1};
 148         # lu_hit[4]: plru_tree[0, 2, 5] = {1, 0, 0};
 149         # lu_hit[3]: plru_tree[0, 1, 4] = {0, 1, 1};
 150         # lu_hit[2]: plru_tree[0, 1, 4] = {0, 1, 0};
 151         # lu_hit[1]: plru_tree[0, 1, 3] = {0, 0, 1};
 152         # lu_hit[0]: plru_tree[0, 1, 3] = {0, 0, 0};
 153         # default: begin /* No hit */ end
 154         # endcase
 155         LOG_TLB = int(log2(TLB_ENTRIES))
 156         for i in range(TLB_ENTRIES):
 157             # we got a hit so update the pointer as it was least recently used
 158             with m.If (lu_hit[i] & self.lu_access_i):
 159                 # Set the nodes to the values we would expect
 160                 for lvl in range(LOG_TLB):
 161                     idx_base = (1<<lvl)-1
 162                     # lvl0 <=> MSB, lvl1 <=> MSB-1, ...
 163                     shift = LOG_TLB - lvl;
 164                     new_idx = Const(~((i >> (shift-1)) & 1))
 165                     m.d.sync += plru_tree[idx_base + (i >> shift)].eq(new_idx)
 166
 167         # Decode tree to write enable signals
 168         # Next for-loop basically creates the following logic for e.g.
 169         # an 8 entry TLB (note: pseudo-code obviously):
 170         # replace_en[7] = &plru_tree[ 6, 2, 0]; #plru_tree[0,2,6]=={1,1,1}
 171         # replace_en[6] = &plru_tree[~6, 2, 0]; #plru_tree[0,2,6]=={1,1,0}
 172         # replace_en[5] = &plru_tree[ 5,~2, 0]; #plru_tree[0,2,5]=={1,0,1}
 173         # replace_en[4] = &plru_tree[~5,~2, 0]; #plru_tree[0,2,5]=={1,0,0}
 174         # replace_en[3] = &plru_tree[ 4, 1,~0]; #plru_tree[0,1,4]=={0,1,1}
 175         # replace_en[2] = &plru_tree[~4, 1,~0]; #plru_tree[0,1,4]=={0,1,0}
 176         # replace_en[1] = &plru_tree[ 3,~1,~0]; #plru_tree[0,1,3]=={0,0,1}
 177         # replace_en[0] = &plru_tree[~3,~1,~0]; #plru_tree[0,1,3]=={0,0,0}
 178         # For each entry traverse the tree. If every tree-node matches
 179         # the corresponding bit of the entry's index, this is
 180         # the next entry to replace.
 181         for i in range(TLB_ENTRIES):
 182             en = [Const(1)]
 183             for lvl in range(LOG_TLB):
 184                 idx_base = (1<<lvl)-1
 185                 # lvl0 <=> MSB, lvl1 <=> MSB-1, ...
 186                 shift = LOG_TLB - lvl;
 187                 new_idx = (i >> (shift-1)) & 1;
 188                 plru = plru_tree[idx_base + (i>>shift)]
 189                 # en &= plru_tree_q[idx_base + (i>>shift)] == new_idx;
 190                 if new_idx:
 191                     en.append(~plru) # yes inverted (using bool())
 192                 else:
 193                     en.append(plru)  # yes inverted (using bool())
 194             # boolean logic manipluation:
 195             # plur0 & plru1 & plur2 == ~(~plru0 | ~plru1 | ~plru2)
 196             m.d.sync += replace_en[i].eq(~Cat(*en).bool())
 197
 198         #--------------
 199         # Sanity checks
 200         #--------------
 201
 202         assert (TLB_ENTRIES % 2 == 0) and (TLB_ENTRIES > 1), \
 203             "TLB size must be a multiple of 2 and greater than 1"
 204         assert (ASID_WIDTH >= 1), \
 205             "ASID width must be at least 1"
 206
 207         return m
 208
 209         """
 210         # Just for checking
 211         function int countSetBits(logic[TLB_ENTRIES-1:0] vector);
 212           automatic int count = 0;
 213           foreach (vector[idx]) begin
 214             count += vector[idx];
 215           end
 216           return count;
 217         endfunction
 218
 219         assert property (@(posedge clk_i)(countSetBits(lu_hit) <= 1))
 220           else $error("More then one hit in TLB!"); $stop(); end
 221         assert property (@(posedge clk_i)(countSetBits(replace_en) <= 1))
 222           else $error("More then one TLB entry selected for next replace!");
 223         """
 224
 225     def ports(self):
 226         return [self.flush_i, self.lu_access_i,
 227                  self.lu_asid_i, self.lu_vaddr_i,
 228                  self.lu_is_2M_o, self.lu_is_1G_o, self.lu_hit_o,
 229                 ] + self.lu_content_o.ports() + self.update_i.ports()
 230
 231 if __name__ == '__main__':
 232     tlb = TLB()
 233     vl = rtlil.convert(tlb, ports=tlb.ports())
 234     with open("test_tlb.il", "w") as f:
 235         f.write(vl)
 236