TLB/test/test_cam_entry.py

   1 import sys
   2 sys.path.append("../src")
   3 sys.path.append("../../TestUtil")
   4
   5 from nmigen.compat.sim import run_simulation
   6
   7 from test_helper import assert_eq, assert_ne, assert_op
   8 from CamEntry import CamEntry
   9
  10 # This function allows for the easy setting of values to the Cam Entry
  11 # Arguments:
  12 #   dut: The CamEntry being tested
  13 #   c (command): NA (0), Read (1), Write (2), Reserve (3)
  14 #   d (data): The data to be set
  15 def set_cam_entry(dut, c, d):
  16     # Write desired values
  17     yield dut.command.eq(c)
  18     yield dut.data_in.eq(d)
  19     yield
  20     # Reset all lines
  21     yield dut.command.eq(0)
  22     yield dut.data_in.eq(0)
  23     yield
  24
  25 # Checks the data state of the CAM entry
  26 # Arguments:
  27 #   dut: The CamEntry being tested
  28 #   d (Data): The expected data
  29 #   op (Operation): (0 => ==), (1 => !=)
  30 def check_data(dut, d, op):
  31     out_d = yield dut.data
  32     assert_op("Data", out_d, d, op)
  33
  34 # Checks the match state of the CAM entry
  35 # Arguments:
  36 #   dut: The CamEntry being tested
  37 #   m (Match): The expected match
  38 #   op (Operation): (0 => ==), (1 => !=)
  39 def check_match(dut, m, op):
  40     out_m = yield dut.match
  41     assert_op("Match", out_m, m, op)
  42
  43 # Checks the state of the CAM entry
  44 # Arguments:
  45 #   dut: The CamEntry being tested
  46 #   d (data): The expected data
  47 #   m (match): The expected match
  48 #   d_op (Operation): Operation for the data assertion (0 => ==), (1 => !=)
  49 #   m_op (Operation): Operation for the match assertion (0 => ==), (1 => !=)
  50 def check_all(dut, d, m, d_op, m_op):
  51     yield from check_data(dut, d, d_op)
  52     yield from check_match(dut, m, m_op)
  53
  54 # This testbench goes through the paces of testing the CamEntry module
  55 # It is done by writing and then reading various combinations of key/data pairs
  56 # and reading the results with varying keys to verify the resulting stored
  57 # data is correct.
  58 def testbench(dut):
  59     # Check write
  60     command = 2
  61     data = 1
  62     match = 0
  63     yield from set_cam_entry(dut, command, data)
  64     yield from check_all(dut, data, match, 0, 0)
  65
  66     # Check read miss
  67     command = 1
  68     data = 2
  69     match = 0
  70     yield from set_cam_entry(dut, command, data)
  71     yield from check_all(dut, data, match, 1, 0)
  72
  73     # Check read hit
  74     command = 1
  75     data = 1
  76     match = 1
  77     yield from set_cam_entry(dut, command, data)
  78     yield from check_all(dut, data, match, 0, 0)
  79
  80     # Check overwrite
  81     command = 2
  82     data = 5
  83     match = 0
  84     yield from set_cam_entry(dut, command, data)
  85     yield
  86     yield from check_all(dut, data, match, 0, 0)
  87
  88     # Check read hit
  89     command = 1
  90     data = 5
  91     match = 1
  92     yield from set_cam_entry(dut, command, data)
  93     yield from check_all(dut, data, match, 0, 0)
  94
  95     # Check reset
  96     command = 3
  97     data = 0
  98     match = 0
  99     yield from set_cam_entry(dut, command, data)
 100     yield from check_all(dut, data, match, 0, 0)
 101
 102     # Extra clock cycle for waveform
 103     yield
 104
 105 if __name__ == "__main__":
 106     dut = CamEntry(4)
 107     run_simulation(dut, testbench(dut), vcd_name="Waveforms/test_cam_entry.vcd")
 108     print("CamEntry Unit Test Success")